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ram: Add support for latch-based memories #10153

Description

@rovinski

Latch-based memories are significantly more efficient than FF-based memories. The ram module should be able to identify whether the -storage_cell is a flip-flop or a latch. If it is the former, the current structure is used. If the latter, a new latch-based array should be used.

A latch-based array is very similar to a flop-based array, except that an additional row of latches is required for each write port. Instead of the input data being connected to a bitcell of each word (usually through an input buffer), the data is instead connected to the D port of a negative (active low) latch first, and then the Q port of this latch is connected to the D port of each bitcell. The bitcell in this case is a positive latch.

I'm not sure if an input buffer should be before or after the latch (or both). It would take some timing analysis to figure that out, which can be a later enhancement.

Activity

  1. added theissue type on Apr 16, 2026
  2. rovinski commented on Apr 16, 2026

    @rovinski
    CollaboratorAuthor

    @tnguy19 this is to track your ongoing latch work.

  3. added a commit that references this issue on Apr 18, 2026
    43dce6f
  4. alokkumardalei-wq commented on Apr 18, 2026

    @alokkumardalei-wq
    Contributor

    Hello @rovinski , @tnguy19 and @maliberty , I have opened a PR for this please have a look when you get time .
    Happy to het any feedback on this further.

    Link to the PR : #10178
    Thank you !

  5. added a commit that references this issue on Apr 18, 2026
    cb2f9a3
  6. tnguy19 commented on Apr 18, 2026

    @tnguy19
    Contributor

    Hi @alokkumardalei-wq thanks for the PR, however this issue is already actively in progress that also can support the ongoing col/mux feature (#10018). If you'd like to help you can check out the feature tracker page for ram, I'd also check if a subissue has been created for a task before starting as that means someone is already working on it

  7. alokkumardalei-wq commented on Apr 18, 2026

    @alokkumardalei-wq
    Contributor

    Hi @tnguy19, thanks for letting me know! I'll close the PR. I didn't realize this was already in progress. I'll check the feature tracker for unclaimed tasks going forward. I'm currently looking at #10152 (decoder verification), happy to help wherever needed.

  8. rovinski commented on Apr 25, 2026

    @rovinski
    CollaboratorAuthor

    @alokkumardalei-wq please read more closely. @braydenlouie is already working on #10152. You can look at any of the other checkbox items in #9392 for issues which have not been started yet.

  9. rovinski commented on Apr 25, 2026

    @rovinski
    CollaboratorAuthor

    Any of the following would be great simple issues to tackle:

    • Add placement sanity checks to the regression tests (check_placement, etc.)
    • Add support for endcap insertion
    • Add automatic detection of standard cell power/ground names
    • Enable optional user-provided name of power rails
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