ram: feature tracker #9392

Description

This is a public tracker for feature development for the ram tool.

• Add support for endcap insertion
  • Endcaps need to be inserted around the perimeter of the RAM bounding box after fill
• Physical verification
  • Check that timing, LVS, and DRC are clean via external tools
• Sweep word and bit sizes 1-64 (all values) to verify support for arbitrary array sizes (no placement or routing errors, LVS clean, DRC clean, passes STA)
• Add support for AND3/AND4 cells in the decoder
  • Only AND2 is supported now. Larger arrays can be more efficient with wider ANDs
• Add support for automatic master selection
  • Find and identify FFs, ICGs, buffers, inverters, tristates, AND2/3/4s automatically if not user specified
• Automatic detection of the followpin metal layer and width
  • The current implementation requires manual specification of the followpin layer and width. This should be automatically extractable from the library. The user should not need to specify this.
• Add support for arbitrary bit mask granularity
  • Currently there is no mask support. Masking support should be added on an arbitrary basis (1 bit, 2 bits, 3 bits, etc.) as long as the word size is divisible by the mask size (cannot make a 2-bit mask for a 7-bit word)
• Add cell anchoring
  • Allow instances within cells to be “anchored” at a certain point, such as for input buffers being aligned with the pins which they drive
• Enable users to specify the input buffer to use, or to even disable completely
  • The current code always inserts a default size buffer. Allow users to manually specify which buffer to use
• Enable users to specify an output buffer to use, or to disable completely
  • The current code does not use an output buffer, which may not be ideal for isolating array timing from the output loads. Add an output buffer by default, but also allow users to specify an output buffer to use or to disable the output buffer.
• Automated test bench support
  • Add an option to automatically generate a testbench and test script for a generated memory. It should run a BIST-style test.
• Formal verification support
  • Add support for using a formal verification tool to verify the RAM behavior
• Add support for metal fill
  • Add an option to provide a fill config and use the built-in metal fill tool to fill the RAM before exporting.
• Banking
  • Add support for multiple banks for very large arrays
  • Add support for clock gating inactive banks
• Add preliminary structured clock tree placement
  • Currently, the clock pin directly fans out directly to all ICGs in the RAM. For small sizes, this is fine, but for larger sizes this can lead to very bad slew and skew. There should be a way to insert clock buffers between either words or columns to break up the large fanout.
• Cross platform testing
  • Add a test for asap7. Would require adding a fake (or real) tristate device as it's not part of the PDK.
• Add support for tapcell insertion intra-cell (currently only supported at word boundaries, potentially leading to more tapcells than necessary)
• Add support for running integrated timing analysis
• Add a user flag to specify the target clock period
  • This flag can be used in combination with timing in order to optimize power/area while still meeting timing constraints.
• Add timing-guided decisions
  • Generate multiple RAM configurations based on user input
  • Use STA APIs to determine whether a certain configuration is better than another (power vs. delay vs. balanced)
  • Example parameters to try: input/output buffer sizes, column mux ratio, banking.
• Investigate support for incremental RAM substitution
  • Consume timing path and constraint information external to the RAM and use it to potentially swap the RAM for a better configuration (e.g. optimize power if meeting timing constraints or vice-versa)
• Investigate support for exporting as multi-height cell / structured placement group
  • Instead of creating a RAM block, the cells could be formed into a placement group which is aligned to the cell grid and fits directly into the core area, bypassing the need for a separate PDN and eliminating the need for block halos/endcaps.
• Add support for automatically determining power grid widths, pitches, and layers, ensuring both routability and acceptable IR drop. Allow the user to manually override.