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ram: add placement sanity checks to the regression tests (check_placement, etc.) #10561
changed the title [-]Add placement sanity checks to the regression tests (`check_placement`, etc.)[/-][+]ram: add placement sanity checks to the regression tests (`check_placement`, etc.)[/+]on May 30, 2026
FYI/notice on this issue. There's a known error that will happen if placement check is added where RAMs with column muxing will have a layer conflict issue with clock gates.
Reproduces on make_8x8_mux2_sky130.tcl with check_placement -verbose:
There's a check in src/dpl/src/infrastructure/network.cxx (lines 98-100):
If a cell has a pin on met1, also reserve met2 above it for via access
Clock gate (sky130_fd_sc_hd__dlclkp_1) CLK pin is on met1, so met2 gets reserved. VDD power stripe also physically sit on met2 at that location leading to this conflict
Other cells (DFFs, buffers) have pins only on li1 which is skipped by this check so no conflict is raised
Routing and functionality still works normally despite this. Will be resolved in a follow-up.
This issue has been automatically marked as stale because it has not had recent activity. It will be closed in 21 days if no further activity occurs. Remove the Stale label or comment to keep it open.
Activity
[-]Add placement sanity checks to the regression tests (`check_placement`, etc.)[/-][+]ram: add placement sanity checks to the regression tests (`check_placement`, etc.)[/+]rovinski commentedon May 30, 2026
@tnguy19
tnguy19 commentedon Jul 7, 2026
FYI/notice on this issue. There's a known error that will happen if placement check is added where RAMs with column muxing will have a layer conflict issue with clock gates.
Reproduces on
make_8x8_mux2_sky130.tclwithcheck_placement -verbose:Cause of issue is currently believed to be:
There's a check in
src/dpl/src/infrastructure/network.cxx(lines 98-100):If a cell has a pin on met1, also reserve met2 above it for via access
Clock gate (sky130_fd_sc_hd__dlclkp_1) CLK pin is on met1, so met2 gets reserved. VDD power stripe also physically sit on met2 at that location leading to this conflict
Other cells (DFFs, buffers) have pins only on li1 which is skipped by this check so no conflict is raised
Routing and functionality still works normally despite this. Will be resolved in a follow-up.
github-actions commentedon Sep 5, 2026
This issue has been automatically marked as stale because it has not had recent activity. It will be closed in 21 days if no further activity occurs. Remove the
Stalelabel or comment to keep it open.