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#1187 scaffolding that stands on main: structured_gen, LEC of clock-gated files, tinyRocket, a blackboxes.txt fix - #1209
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tools/structured_gen is the bazel-orfs copy of what moved into OpenROAD as generate_regfile (patch 0010, OpenROAD#11669). Main's 0010 has three changes the tool lacks; the tool takes them: - A netlist-mode abstract's pins sit at the centroid of the cells on their net -- a write data bit over its column's write muxes, a read data bit at its bitline's root, an address among its inverters and decode -- snapped to the track grid as the edge pins are (rtl_macro_placer refuses an off-grid pin, MPL-0005). The parent's macro placer flips a macro to shorten the wires to its pins; edge pins packed in a corner said nothing about where those go. They are never routed: the block dissolves first. - The port check read one port per line and missed `input [4:0] ra1, ra2, wa3`, riscv32i's register file. It reads the header per comma entry, a bare name inheriting the direction and width before it, and strips block comments. - The views and the netlist name the command, not the tool. regfile_test checks both: riscv32i's header read port by port, and a write data pin within its column, every pin in the die. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
…t out //test/structured_gen_lec checks generate_regfile (OpenROAD patch 0010) against yosys's synthesis of the RTL on the comb, fp, int and vf fixtures, in both write styles. A clock gate per word puts the write enable on the clock, and kepler-formal makes an integrated clock gate's latch opaque on purpose, so the clock-gated netlist could not be checked at all. Carried kepler-formal patch 0002, experimental and not upstreamed: --skip-gated-clock-flops leaves out the inputs of a flop whose clock pin is driven by a cell output with no truth table but a combinational dependency (an ICG's GCLK), warns with the count, lists them in skipped_gated_clock_pos.txt, and compares the rest: every read, through every flop's output. lec_test's skip_gated_clock_flops passes it and requires the warning. A clock-gated twin of fp8_unregistered shows the skip hides no read-path bug: it is still caught. 21 of 21 pass. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
… +3.6 %, placed files beat inlined T1, #1187 at f681c30 from source: Frontend 2,170 -> 1,792 ps and VecRegionModule 1,479 -> 1,278 with generate_regfile's new read path, FltRegionModule 895 -> 951, the parent 3,276 ps (row 12 3,162, entry 48 3,386). The zero-wire census puts the parent's floor lowest of the four measured (2,021 ps); the loss is wire and repeaters, #1184's mechanism in part. T2b, the parent's three files inlined on the same plan: 3,529 ps and 29 % congestion, so the planned, dissolved files stay. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
asap7/tinyRocket, ORFS's AUTO_MEMORIES design, had not canonicalized: the Rocket Chip generator leaves its cache memories as black boxes (data_arrays_0_ext, data_arrays_0_0_ext, tag_array_ext), the generic sources define none, and AUTO_MEMORIES only detects a memory yosys infers. Only tag_array, forced by an override, got a macro; data_arrays_0_ext was "not part of the design". Under slang the memory extraction stopped earlier on the same unknown modules. Nothing built the design, in ORFS CI (nangate45's tinyRocket maps the memories by hand) or here (auto_memories_outputs_test only analyses it). ORFS patch 0092 adds behavioral models of the three in firtool's read-write convention: the two data arrays become FakeRAM macros, the 4 x 25 tag array flip-flops by the gate's own choice, and its override goes. It also carries the design's README. tinyrocket_synth_build_test builds the synthesis, detection and macro generation included. 0092 is The-OpenROAD-Project/OpenROAD-flow-scripts#4643 at its head, review changes included; it retires at a bump onto an ORFS that has it. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
ORFS patch 0090 (OpenROAD-flow-scripts#4650) writes `<module> <area>` per line of blackboxes.txt, so synthesis can cost a macro's blackbox. check_memories_applied.py read the whole line as the module name and looked for an instance of `<module> <area>` in the netlist, a module no netlist has. It reads the first field. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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Five commits from #1187 that stand on main by themselves, each applying to
origin/mainalone. They are scaffolding while the register-file work settles in OpenROAD and ORFS; landing them shrinks #1187 to the register-file study itself.input [4:0] ra1, ra2, wa3); the views naming the command.--skip-gated-clock-flops. Carried kepler-formal patch 0002, the same code as Experimental: --skip-gated-clock-flops, so a clock-gated netlist can be checked, minus its gated flops keplertech/kepler-formal#274 (which also adds a unit test of kepler-formal's own).lec_testgainsskip_gated_clock_flops;//test/structured_gen_lecchecks generate_regfile in both write styles, a clock-gated twin offp8_unregisteredshowing the skip hides no read-path bug.tinyrocket_synth_build_test.<module> <area>, and the check looked for an instance of the whole line.Tested:
fix_lint,public_surface,host_tools,build --nobuild //...;//tools/structured_gen/...,//test/coremark_joule/scripts/...,//test/lec/..., the generate_regfile LEC tests,tinyrocket_synth_build_testandauto_memories_outputs_testpass.🤖 Generated with Claude Code