AUTO_MEMORIES_REGFILES: register files as macros that dissolve after macro placement

[oharboe]

Draft, scaffolding: not for merge as is. This is the integration branch for register files built as placed standard cells (AUTO_MEMORIES_REGFILES). The feature lands upstream, piece by piece. The pieces are carried here as patches so they can be exercised together on real designs. Each patch retires at the //:bump onto the upstream that carries it, and is left as it is while its upstream pull request settles (upstream-pr, section 6). CI does not have to pass.

Upstream

Piece	Carried here	Upstream
generate_regfile: the array as placed standard cells	OpenROAD patch 0010	OpenROAD #11669
AUTO_MEMORIES_REGFILES, AUTO_MEMORIES_MACRO_PLACE, the dissolve after macro placement	ORFS 0089, 0091	ORFS #4651 (draft)
A generated macro's blackbox costs its view's area	ORFS 0090	ORFS #4650
tinyRocket's memories modelled	ORFS 0092	ORFS #4643
SYNTH_VERILOG_SURGERY	ORFS 0094 (from main)	ORFS #4649
coralnpu's register file	ORFS 0102, 0103	ORFS #4653 (draft)
memory <module>.<cell>: a seam yosys makes for an inline array	ORFS 0093	none yet
kepler-formal skips flops behind a clock gate, so the clock-gated register file can be checked	kepler-formal patch 0002	none yet
Ladder designs: picorv32, ibex, swerv, cva6, the riscv32i modes and seeds, the mux variants	ORFS 0095-0100, 0104, 0105	not proposed: campaign only

What is here to work on it

• test/regfile: dissolve, clocking and grt build tests, and the register file in simulation.
• test/structured_gen_lec: generate_regfile checked against its RTL by kepler-formal.
• test/regfile/ladder: each design with its register file in each generate_regfile mode, its simulation, and the surgery that gives an inline array a module.
• test/regfile/campaign: the riscv32i clock-period campaign, paused for a bigger machine. The state and the claims it supersedes are in the reseat comment and test/regfile/campaign/results.md. Numbers in this pull request's earlier comments are superseded there.

Rebased onto main

• 0094 is main's, the net diff of ORFS #4649, listed once.
• 0072 and 0079 retired on main at the bump onto ORFS ef421749.
• "designs: a design directory gets its own config" is main's; the ladder keeps its own test of it over its variant designs.
• SYNTH_POST_HIERARCHY_SCRIPTS is no longer a source variable: no design here sets it in a config.mk any more, and as one it failed the variables.yaml check for veer, so no package loaded.

🤖 Generated with Claude Code

[oharboe]

Fewer register files that need a seam in the RTL

Seams are still needed, but yosys can make one for any register file it
infers as a $mem_v2. That leaves fewer cases that need a hand-made seam.

Category	Examples (from AutoMemories.md)	Seam
Own module, ports a spec can name	riscv32i regfile	spec, today
Inferred as $mem_v2, anywhere in the hierarchy	picorv32 cpuregs; to check: tinyRocket, coralnpu Regfile/FRegfile, swerv dec_gpr_ctl	yosys makes it, no RTL change
Array with a reset	ibex ibex_register_file_ff, cva6 ariane_regfile_ff	needs one in the RTL
Chisel Reg(Vec)	XiangShan	needs one in the RTL: by default firtool splits it into one register per element plus mux trees, so yosys never sees an array

How yosys makes the seam. The passes are memory_libmap and then
techmap. This is how FPGA flows put an inline array into a block RAM
(passes/memory/memlib.md).

• memory_libmap turns each matching $mem_v2 into a $__<name> cell,
  and techmap turns that cell into an instance of the generated macro.
• Anything the RAM definition doesn't describe stays in the parent as
  logic: x0 reading 0, bypass, scoreboard, read enables. That's what
  keeps coralnpu's and swerv's register files out of a spec today.
• memlib's ar port kind describes the combinational reads register
  files have.

One RAM definition per memory. gen_memories.py would write, from
memories_inferred.json:

• a memlib ram block for each accepted memory, with its own abits,
  width, ports, and style "<macro>";
• a techmap wrapper for each block, naming the pins generate_regfile
  builds.

setattr ram_style=<macro> on each accepted $mem_v2 makes it map only
to its own macro. Unlisted memories still become flip-flops through
memory_map.

Where it goes in synthesis. In synth.tcl, between synth -run :fine
and synth -run fine:. That's where SYNTH_MOCK_LARGE_MEMORIES already
works on $mem_v2: after memory_dff, before memory_map.

Opt-in by name. List each memory by its inventory name,
<module>.<cell>. 0066 would still refuse any array that isn't listed.

Open:

• The main synthesis has to see the same $mem_v2 the extraction run
  inventoried, with the same name and shape. It runs opt and
  memory_share that the scoped extraction (0079) doesn't, and slang's
  uniquified names (0081) have already broken name matching once. A
  listed memory that doesn't map should stop the build.
• The dissolve hasn't been checked with the instance sitting in the CPU
  module instead of in a module of its own.

Not measured. The cheap test is picorv32's cpuregs: one hand-written
memlib entry and techmap wrapper, then count flip-flops before and after.
That takes seconds.

[oharboe]

Some data for OpenROAD's ram tracker (OpenROAD #9392) from an experiment on asap7, and questions
before going further.

Claude made the changes and I stared at paint drying: a register file of
placed standard cells for ORFS's riscv32i (32 x 32, 2R1W), to try three
items from that tracker in a full flow: asap7 support, the AND2 decoder,
and exporting the array as cells on the core's rows rather than as a
block. Neither of us read RamGen first, so it ended up as a separate
generator, carried as a patch in a test scaffold. That's the wrong place
for it. RamGen is the generator, and I'd like to carry as little as
possible on top of it.

riscv32i to global route, 950 ps clock, global-route parasitics:

	flip-flops	placed register file
minimum period	954 ps	998 ps
failing endpoints	79	992, all in the array

The worst path goes through the decode as three serial AND2 stages, then
an OR2 tree: 232 ps from instr to read data. Placed as a macro and then
dissolved into fixed cells on the core's rows, the array reaches global
route with no PDN or halo of its own.

Questions:

1. asap7 has no tristate. Would you rather have a fake tristate cell in
   the platform, as the tracker suggests, or an AND/OR read path in
   RamGen?
2. For "export as a structured placement group": should RamGen place the
   cells into the parent's rows itself, or write a placed block that the
   flow dissolves after macro placement, as we did?
3. Is a 2R1W register file in scope for RamGen, or does it belong in a
   different tool?

[oharboe]

Plan: from this PR to upstream

This PR is integration testing. It carries every change as a patch and
runs them in full flows. The changes go upstream as small pull requests,
the base first, and each one links here for the full-flow evidence. When
the last one merges and //:bump moves onto it, the patches are retired
and nothing is carried.

Extend generate_ram; no new command

OpenROAD's generate_ram (src/ram) already builds a memory from
standard cells: decoder column, tap columns, rows, LEF/DEF, a netlist-only
variant (generate_ram_netlist), and options that swap parts of the bit
(-use_latch, -column_mux_ratio). Two things in its bit stop it from
building these register files:

• Writes: each bit's flop takes the column's shared data line and is
  written through a per-word clock gate, so there is one write port
  (read-write plus write ports must sum to 1).
• Reads: one tristate per read port on a shared bit line. asap7 has
  no tristate cell.

Patch 0010's generate_regfile solved both as a separate command (a
write select per bit; an AND per read port and OR trees). Upstream, they
become options on generate_ram, and 0010 retires.

Upstream stack

#	Repo	Change	Needs
1	OpenROAD	generate_ram: an AND/OR read path in place of tristates, with an asap7 test	—
2	OpenROAD	generate_ram: more than one write port, a write select per bit in place of the clock-gated write	1
3	OpenROAD	generate_ram: decode and read trees sized for their fanout (AND3/AND4, AO22, NAND/NOR)	1
4	ORFS	AUTO_MEMORIES_REGFILES: a spec per module mapped onto generate_ram options, blackboxed and placed like an AUTO_MEMORIES macro	2
5	ORFS	the dissolve after macro placement: the macro becomes FIRM cells on the core's rows	4

Spec-only features (RTL port names, zero_word, banks, bit folds) live
in ORFS's mapping (4), not in OpenROAD's arguments, unless a reviewer
wants them there.

Upstream pull requests are opened by a human. This PR stays a draft
until 1 has merged.

Gate: riscv32i must win

riscv32i is the fast-turnaround baseline: it reaches global route in
minutes. Today the generated register file loses to flip-flops:

to global route, 950 ps clock	flip-flops	register file
minimum period	954 ps	998 ps
failing endpoints	79	992
core area	4 012 um²	7 573 um²

The worst path runs through the decode as three serial AND2 stages and
an OR2 read tree: 232 ps from instr to read data.

Experiments to find a structure that wins can continue on 0010, where
the turnaround is already set up. The proof each upstream pull request
links to is riscv32i built with generate_ram and that pull request's
options: minimum period at or below flip-flops', with area reported.

Why register files need this

XiangShan's register files are Reg(Vec). yosys never infers a memory
from them, and it does not finish synthesising them as flip-flops at
this size:

Register file	Words × bits	Ports
IntRegFile	224 × 64	12 banked reads, 9 writes
FpRegFile	256 × 64	14 reads, 7 writes
VfRegFile	128 × 128	14 reads, 7 writes
RobEntryFile / RenameBufferFile	352 × 21 / 20	16 reads, 8 writes

Rules for the upstream pull requests

• One concern per pull request; each one builds, tests and is useful on
  its own.
• With the new options off, generate_ram's existing sky130 and
  Nangate45 tests pass unchanged.
• New tests assert intent and pass or fail: ports as asked, every cell
  placed, no overlaps, reads and writes correct in simulation of the
  behavioral model against the netlist. No new golden .defok, .lefok
  or .libok files.
• The description gives the evidence and links here.

[oharboe]

Reseat: the riscv32i register-file campaign

Paused here to carry on on a machine that can run several experiments
at once. Everything needed is on branch regfile/campaign-wip
(68178d9), five commits on this PR's head, not merged into it:

commit	what
52b09b9	dissolve: cut the rows around macros before the array is FIRM (cut_rows skips a row holding a fixed cell, ODB-0386; an endcap landed inside a FakeRAM), FLW-0014 if a cell is off-row
6a69961	generate_regfile: read bitlines as an AOI22 per word pair and a NAND2/NOR2 tree, OR2 at the root
e5dcafd	generate_regfile: tile width from simulating the row fill (46 -> 30 sites on riscv32i); write-mux cell count fixed
9967f88	riscv32i-regfile: flat array (bit_folds 1) at riscv32i's own 62 %
68178d9	test/regfile/campaign/: results, the scripts, generator variants, the lined-up experiments

Results so far (global route, 950 ps clock)

configuration	min period	core um2	std cells um2
flip-flops (the gate)	954	4012	1284
flip-flops at 45 % (control)	951	5533	1273
this PR's head	998	7573	1413
this PR's head, array unfixed (control)	999	7573	1411
+ AOI22/NAND/NOR read tree, folds 2, 45 %	977	7353	1190
+ 30-site tiles, flat, 62 %	1003	4466	1161
+ 30-site tiles, flat, 45 %	982	6156	1116
+ 30-site tiles, folds 2, 35 %	973	8055	1170

Nothing reaches parity yet. The register file is 7-13 % smaller in
standard cells than the flops in every configuration. The trade is
shape: a folded array is faster (half-length select lines; the flat 53
um ones take three BUFx12f), a flat one fits a flip-flop-sized core.

Disregard in this PR's description and earlier comments

These are superseded or wrong; test/regfile/campaign/results.md on the
branch replaces them:

1. The riscv32i tables (998 ps, 7 573 um2, 1 413 um2) in the
   description, in the comment for OpenROAD #9392 and in the plan's
   "Gate" section: superseded by the table above.
2. "232 ps from instr to read data", "three serial AND2 stages, then
   ... five OR2 levels" as the reason it is slower: with the
   AOI22/NAND/NOR tree the read path is off the critical path in most
   runs. Three serial AND2s remain in the decode and still matter on the
   flat array.
3. "cells the resizer may swap in place" as a fix, and any reading
   that FIRM or dont_touch costs timing: the unfixed control (999 vs 998
   ps) shows it costs nothing. The netlist structure is what mattered.
4. "The core is bigger because config.mk sets 45 %": the cause was
   the tile width estimate padding every tile by a flop's width; with
   30-site tiles the flat array fits riscv32i's 62 %.
5. The same text is in docs/user/AutoMemories.md inside patch 0089;
   it is stale on this PR's head and not yet rewritten on the branch.

Still correct: asap7 has no tristate cell (no three_state pin in any
RVT standard-cell library), and the memlib comment is an unmeasured
proposal, as it says.

Not verified on the branch

• The goldens in src/ram/test (generate_regfile_asap7.*ok) are not
  regenerated after 6a69961; OpenROAD's ram tests cannot be analysed
  from bazel-orfs (they need an @llvm repository). Regenerate with
  OPENROAD_SRC=<OpenROAD checkout> test/regfile/campaign/golden.py <openroad>.
• Run on the branch: the LEC suite (12/12 after 6a69961; e5dcafd does
  not change the netlist), //test/regfile:{regfile,riscv32i}_clocked_test,
  riscv32i-regfile to global route (each row above), fix_lint,
  public_surface, host_tools. Not re-run on the branch head:
  //test/regfile:check_dissolve_test,
  //test/regfile:regfile_grt_build_test, //test:all,
  //test/planned_parent:all.

To carry on

test/regfile/campaign/README.md has the commands. One worktree per
lane: a lane builds from the patches in its own checkout, so two lanes
in one worktree change each other's inputs mid-run. A riscv32i run to
global route is about 10 minutes and under 1 GB.

Lined up, in parallel:

1. Predecode (predecode.diff) on flat 45 %: one serial AND2 less
   on the select path.
2. Dissolve, then unplace at 62 % (unplace.tcl): free placement of
   the better netlist.
3. Never a macro: riscv32i with regfile.v replaced by the generated
   netlist, the core sized from the real cell area.
4. Shape annealer at floorplan, before macro placement: register-file
   shapes with unchanged ports, the FakeRAMs, channels and the real
   standard-cell area; the chosen shape generated there and swapped in
   with swapMaster; mode netlist only. It must weigh select-line
   length as well as area.
5. Write side: a clock gate per word instead of the per-bit AO22 hold
   mux, as generate_ram does. It changes CTS: decide before building.

Word groups (word-groups.diff, two words sharing a bit column's rows)
narrow the tiles 30 -> 26 sites; measured, not taken.

🤖 Generated with Claude Code

[oharboe]

riscv32i register-file campaign: a clock gate per word reaches the flip-flops

Branch regfile/campaign-wip at 060865e, five lanes in parallel. Global route, 950 ps clock.

configuration	min period	core µm²	std cells µm²
flip-flops (the gate)	954	4012	1284
flip-flops at 45 % (control)	951	5533	1273
AOI22/NAND/NOR read, 30-site tiles, flat, 45 % (before)	982	6156	1116
predecode, flat, 45 %	1000	6106	1112
dissolved, then placed freely, flat, 62 %	1012	4466	1171
never a macro, 62 %	994	3770	1144
write clock gate, flat, 45 %	951	5687	962
write clock gate, flat, 55 %	959	4644	980
write clock gate, flat, 62 %	MPL-0003
never a macro + write clock gate, 62 %	955	3544	973

The write clock gate is the change that reaches the flip-flops. Each word gets one ICGx1, enabled by its write select, in place of the per-bit AO22 hold mux. This is how generate_ram already writes.

• With one write port, a flop's D is the write data bit itself.
• Array endpoints that miss timing fall from 920 to 7.
• Standard-cell area is 25 % under the flip-flops'.

Never a macro is the shape that wins on area. riscv32i reads the generated netlist in synthesis in place of regfile.v. Its cells are placed and sized like any others: no macro tiling, no dissolve. With the write clock gate it reaches 955 ps against the flops' 954 (parity) on a core 12 % smaller. As a macro, the smaller netlist does not fit riscv32i's 62 %.

Negatives:

• Predecode: its xp33 select drivers need three buffers on the 53 µm select line.
• Dissolving the array and then placing it freely: no faster than keeping it fixed.

Not verified:

• The clock-gated array's function: there is no simulation or equivalence check of generate_regfile's output yet. //test/structured_gen_lec checks the other generator.
• Hold, clock power and CTS with 31 gated clocks.
• The src/ram/test goldens, which still lag.
• //test/regfile:all passes, including riscv32i_clocked_test with the clock gate: every register is clocked at floorplan.

Next, if this direction holds: never a macro as a flow mode. The memories step would hand synthesis the generated netlist in place of the module. That would retire the dissolve and its row cutting rather than add to them. It changes this PR's design, so it waits for your call.

🤖 Generated with Claude Code

[oharboe]

generate_regfile checked by LEC, clock-gated flops included

//test/structured_gen_lec now also checks OpenROAD's generate_regfile against yosys's synthesis of the RTL. It runs on the comb, fp, int and vf fixtures (banked and interleaved reads, the zero word, registered reads, up to 7 write ports), in both write styles. 21 of 21 pass.

The clock gate per word needed a carried kepler-formal patch. kepler-formal makes an integrated clock gate's latch opaque on purpose, so a clock-gated netlist could not be checked at all.

Patch kepler-formal-0002 is experimental and not upstreamed. It adds --skip-gated-clock-flops, which:

• leaves out the inputs of each flop whose clock pin is driven by a cell output with no truth table but a combinational dependency (an ICG's GCLK);
• warns with the count and lists the skipped flops in skipped_gated_clock_pos.txt;
• compares everything else, i.e. every read, through every flop's output.

The write enable is the one thing it does not prove. test/regfile/sim covers that by simulation.

A clock-gated twin of fp8_unregistered, a read-address bug, is still caught, so the skip hides no read-path difference.

It is meant as a strong signal for automated loops, not as production sign-off.

🤖 Generated with Claude Code

[oharboe]

Register-file ladder: ORFS's asap7 designs with a register file

test/regfile/ladder runs each design against a -regfile variant (carried ORFS patches) to global route. A row passes when the register file's minimum period is at most 3 % above the flip-flops'. The period is ORFS's own timing__fmax__clock:<name> for the slowest clock, port paths included; a reload of each arm's global-route ODB gives the same numbers. Both arms of every measured row have the same macro count.

design	register file	route	min period, flops / regfile	std-cell area	power
riscv32i	32×32, 2R 1W	module spec	923 / 922 ps (−0.1 %)	−24.0 %	−24.1 %	passes
picorv32	32×32, 1R 1W	seam (0093)	3 seeds: mean 444 / 450 ps (+1.4 %)	−4.3 %	−9.3 %	passes on its noise band
ibex	32×32, 2R 1W, async reset	module spec	970 / 960 ps (−1.0 %)	−9.8 %	−33.2 %	passes
tinyRocket	32×32, 2R 1W	seam (0093)	1282 / 1171 ps (−8.7 %)	−4.7 %	−21.2 %	passes
swerv_wrapper	32×32, 4R 3W, async reset	surgery + module spec	1297 / 1299 ps (+0.2 %)	+0.6 %	+3.6 %	passes
cva6 (cv32a65x)	32×32, 4R 2W, async reset, later write wins	surgery + module spec	—			blocked, see below

picorv32 at GPL_RANDOM_SEED 1, 2 and 3: +4.0 %, +3.4 %, −3.3 %. Each arm spreads by about 4 % across seeds; the single-seed difference was placement noise. Its worst paths in both arms are the multiplier's adder chains, not the register file.

swerv is the one row where the register file costs area and power: its flip-flop baseline already gates the clock per word, and its 992 reset flops are larger cells.

What the ladder added

• OpenROAD 0011 async_reset <port> low|high: storage that resets to zero (DFFASRHQNx1, set tied off per word).
• OpenROAD 0012: the port check reads SystemVerilog headers (#(...), widths in parameters, packed dimensions) and stops on a declaration it cannot read; unused <port>.
• OpenROAD 0013 write_priority last: the later write port wins a collision (cva6's two commit ports).
• ORFS 0094 SYNTH_VERILOG_SURGERY: a script edits copies of the sources before synthesis. Documented as a hack.
• ORFS 0095–0098: the picorv32, ibex, swerv and cva6 variants. 0099: an inlined register file in place of a parameterized module. 0100: picorv32's seed variants.

Evidence that the register files compute what the RTL does

bazelisk test //test/regfile/ladder:all, nine tests:

• Each spec's generated netlist against the RTL module it replaces, or against a behavioural memory for a seam spec: 20 000 random cycles with reads, writes and resets.
• swerv and cva6: the module before and after surgery, with the register file as generated: 20 000 cycles, 38 and 41 resets, 0 mismatches. cva6's colliding writes are driven, so write_priority last is exercised.
• A negative control (ibex's spec with its reset dropped) must mismatch, and does.

Two findings outside the register file

• ORFS's aggregate timing__fmax metric is the maximum over clocks. riscv32i, ibex and picorv32 have a virtual I/O clock whose fmax is the more optimistic one, so the aggregate understates the period: ibex's read 807 ps against 970 ps for core_clock. The rows read the per-clock metrics.
• ORFS never defines OPENROAD_CLKGATE, so the platform's OPENROAD_CLKGATE is a wire and every rvdffe word in swerv_wrapper reloads on every clock: its register file holds no value. Both swerv arms here define it (asap7/swerv_wrapper-yosys), so the flip-flop baseline is the gated register file SweRV's source describes. Both arms go through yosys, because the register-file inlining exists only there and swerv_wrapper itself uses SYNTH_USE_SYN.

Open

• cva6: ORFS's own asap7/cva6, the flip-flop baseline, stops in slang's elaboration inside the Bazel sandbox ("Compilation failed", no diagnostic printed), while the same read succeeds outside Bazel. Its surgery and simulation are verified; the row waits on the baseline.
• coralnpu: Regfile (8R 6W) and FRegfile (3R 2W) are flops among scoreboard and bypass logic; they need a surgery script of their own.
• At global route, ibex's register-file arm spends most of its time in repair_timing's endpoint loop (incremental reroute and STA). Recorded, not gated.

Rows: bazelisk build //test/regfile/ladder:<design>_row. Worst paths per arm: //test/regfile/ladder:<design>_{flops,regfile}_paths.

[oharboe]

@maliberty FYI: this PR is the integration test for a register-file feature that spans OpenROAD and ORFS. It shows the OpenROAD and ORFS changes working together on ORFS's own designs.

TL;DR: a register-file generator, generate_regfile, built on the RAM generator. It replaces flip-flop register files in ORFS designs with a structured standard-cell array. Across ORFS's asap7 cores it holds the clock period within noise, cuts standard-cell area by up to 24 % and power by up to 33 %, and simulation shows each one computes what the RTL does.

design	register file	min period, flops → regfile	std-cell area	power
riscv32i	32×32, 2R 1W	923 → 922 ps (−0.1 %)	−24.0 %	−24.1 %
ibex	32×32, 2R 1W, async reset	970 → 960 ps (−1.0 %)	−9.8 %	−33.2 %
tinyRocket	32×32, 2R 1W	1282 → 1171 ps (−8.7 %)	−4.7 %	−21.2 %
picorv32	32×32, 1R 1W	444 → 450 ps (+1.4 %, mean of 3 seeds)	−4.3 %	−9.3 %
swerv_wrapper	32×32, 4R 3W, async reset	1297 → 1299 ps (+0.2 %)	+0.6 %	+3.6 %

Global route, each design's own config and clock; the period is the slowest clock's, port paths included. In every measured design the generated register file matches the RTL it replaces, simulated under random reads, writes and resets.

Synthesis time. Trivial for these examples. Yosys synthesis (1_2_yosys): ibex 41 → 28 s, picorv32 33 → 29 s, tinyRocket 46 → 41 s.

On XiangShan, synthesis with flip-flop register files ran forever. With this feature it completes. Together with parallel hierarchical synthesis and macros, XiangShan's run time is tolerable: overnight. I haven't studied exactly where the time went, and don't plan to: measuring "forever" would take days or weeks.

OpenROAD

• generate_regfile in src/ram, built on the RAM generator. Multi-port, an integrated clock gate (ICG) per word, async reset, write priority. It checks its ports against the RTL module it replaces.

ORFS

• AUTO_MEMORIES_REGFILES: lists the register files to generate. Each is inlined (placed and sized with the rest of the design) or placed as a macro.
• Yosys seams: most cores keep the register file as an inline array with no module of its own (Rocket, picorv32). Synthesis cuts a module around the memory yosys infers there, and the generated register file replaces it. The RTL is never edited.
• SYNTH_VERILOG_SURGERY: a deliberately hacky pre-synthesis hook. A script edits copies of the sources before yosys reads them: it carves out a register file yosys can't infer (swerv, cva6), ties off test bits, and so on. In my own flows that step lives in Bazel; this gives a make-based ORFS flow the same hook without Makefile hacking.

Here both are carried as patches on OpenROAD and ORFS. Details and open items are in the comment above.

[oharboe]

cva6 (cv32a65x), the last rung: passes. Rebased on main, which now carries #1200: the flip-flop baseline used to stop in slang's elaboration in the Bazel sandbox because a generated BUILD file hid common_cells/registers.svh from cva6's include group.

design	register file	min period, flops → regfile	std-cell area	power
cva6 (cv32a65x)	32×32, 4R 2W, async reset, later write wins	909.5 → 909.8 ps (+0.03 %)	14,458 → 13,900 µm² (−3.9 %)	185.1 → 159.2 mW (−14.0 %)

Global route, ORFS's own asap7/cva6 config and clock against the cva6-regfile variant (surgery + module spec, write_priority last); 8 macros in both arms. Run time to global route: 1,698 → 1,550 s, synthesis 483 → 454 s.

Correctness: on the rebased branch all 9 ladder tests pass, including cva6_surgery_test (ORFS's ariane_regfile against the surgered one with the generated register file, colliding commit-port writes driven) and cva6_sim_test.

With cva6, every design on the ladder passes: riscv32i −0.1 %, ibex −1.0 %, tinyRocket −8.7 %, picorv32 +1.4 % (mean of 3 seeds), swerv_wrapper +0.2 %, cva6 +0.03 %.

Also in the rebase: row.py now counts global route in a row's stage times; it used to leave the grt log out of the total.

[oharboe]

coralnpu, rung 7: passes, and it's the first rung where the wrapper around the register file mattered.

coralnpu (CoreMiniAxi), global route	flops	regfile
min period	2,009 ps	1,899 ps (−5.5 %), meets the 1,900 ps target, so a bound
setup TNS	−93,647 ps	0
std-cell area	16,525 µm²	15,487 µm² (−6.3 %)
power	33.0 mW	35.8 mW (+8.5 %)
stage time, total	4,514 s	1,072 s (4.2× less)

Register file: Regfile, 32×32 with 8 reads and 6 writes (twice the ports of any earlier rung), x0 zero, async reset high, colliding writes ORed.

An idiomatic baseline first (ORFS 0102). ORFS's asap7/coralnpu had problems of the flow's own making, fixed here without touching the snapshot:

• a 10 ps clock (ORFS's rules file implies about 2.04 ns achieved); the SDC now uses the platform's constraints.sdc at 1,900 ps, with io_te held at 0 and the async reset not timed;
• USE_ASAP7 fakerams with no write mask, so every masked write wrote all 16 bytes; surgery now turns each TCM SRAM into a firtool read-write memory module, and AUTO_MEMORIES generates masked macros;
• firtool's verification layers concatenated in (61 binds); surgery strips them, which is firtool's output without layers;
• ClockGate left as a latch and an AND; it now maps onto ASAP7's ICG through SYNTH_POST_HIERARCHY_SCRIPTS (0101 declares the variable);
• the kept hierarchy is now coralnpu's units by name (SYNTH_KEEP_MODULES, OPENROAD_HIERARCHICAL=1).

CoreMiniAxi.sv is unchanged: the adaptation is a config, an SDC, a surgery script, a yosys script and a spec.

Two iterations (0103). The first moved Regfile's 31 words into Regfile_rf and nothing else:

• period −0.2 %, but area +1.7 %, power +9.5 %;
• global route stopped after more than 8,800 s, against 1,322 s for flops.

Regfile's read bypass selected among all 31 words' decoded write data, and that decode now fed nothing but the bypass. The second iteration rewrites the bypass as a write-through read: the read address compared with each write port's address, using only the register file's ports. That gives the table above. The pattern applies to any dissolved register file; the generator stays plain storage.

Where the time goes. In the flip-flop arm, repair_timing is 3,369 s of 4,514 (75 %): 2,421 s inside CTS (clock_tree_synthesis itself takes 16 s) and 928 s inside global route, chasing a target the design does not reach. In the register-file arm, which meets it, repair takes 83 s. The flip-flop arm, re-run, reproduced its QoR exactly (TNS −93,646.7 both times); its CTS time moved 2,181 → 2,562 s.

Correctness. All 13 ladder tests pass. The coralnpu ones:

• coralnpu_surgery_test: Regfile as ORFS has it against the surgered one with the generated array, 20 000 random cycles, colliding writes on six ports, masks, readSet, bypass, resets;
• coralnpu_sim_test: the spec against the behavioural register file;
• coralnpu_write_last_sim_test: a negative control (later write wins) that must mismatch, and does;
• coralnpu_synth_test: checks the build is what 0102 says.

Open: the +8.5 % power, where clock skew also rose (306 → 415 ps), points at the per-word clock gates. And the repair long tail: ORFS runs repair_timing without per-iteration progress, so finding where repair stops paying needs a run with it.

[oharboe]

A correction, a bug fix, and clock gate vs mux per word.

Bug: two design directories that shared a DESIGN_NICKNAME shared a config. @orfs_designs keyed DESIGNS by nickname, so a variant that includes its base's config.mk replaced the base's entry. Since the seed variants, asap7/picorv32-regfile ran picorv32-regfile-seed3's config (GPL_RANDOM_SEED 3). Fixed in private/designs.bzl: the directory key always holds the directory's own config. designs_by_directory_test checks it and fails on the old keying. Only this PR's variants shared a nickname, all asap7.

Correction: picorv32's seed band. The earlier mean of +1.4 % counted one register-file arm twice. Re-run, all three seeds on one ORFS:

picorv32	flops	regfile	Δ period	Δ area	Δ power
seed 1	443.35 ps	445.13 ps	+0.4 %	−4.1 %	−8.8 %
seed 2	462.64 ps	443.48 ps	−4.1 %	−4.9 %	−10.1 %
seed 3	434.10 ps	451.02 ps	+3.9 %	−6.0 %	−12.0 %
mean	446.7 ps	446.5 ps	−0.03 %

Clock gate per word or mux per word (write_style; ORFS 0104 adds -mux variants):

design		flops	clock gate	mux
swerv_wrapper	power	84.5 mW	87.1 mW (+3.1 %)	78.8 mW (−6.7 %)
	area	17,123 µm²	17,281 µm²	17,188 µm²
	period	1,293 ps	1,299 ps	1,298 ps
coralnpu	power	63.3 mW	45.4 mW (−28 %)	52.1 mW (−18 %)
	area	16,563 µm²	15,512 µm²	15,743 µm²
	clock skew		~400 ps	73 ps

The better style depends on the design: muxes for swerv, clock gates for coralnpu. So write_style is a per-design choice in the spec, not a default to fix. Power is estimated without switching activity; read it with that caveat. The skew cost of a clock gate per word is structural, though: many small gated subtrees under CTS.

coralnpu's numbers are now as ORFS draft The-OpenROAD-Project/OpenROAD-flow-scripts#4653 has it, without the ClockGate mapping onto ASAP7's ICG. The flip-flop arm reproduced its QoR exactly across two runs.

[oharboe]

riscv32i in each generate_regfile shape (ORFS 0105, rows riscv32i_netlist and riscv32i_macro), one run each:

riscv32i	period	std-cell area	power	stage time
flops	907 ps	1,289 µm²	31.1 mW	228 s
inlined	922 ps (+1.6 %)	985 µm² (−24 %)	23.9 mW (−23 %)	180 s
mode netlist (macro-placed, then dissolved)	951 ps (+4.9 %)	1,006 µm² (−22 %)	24.3 mW (−22 %)	166 s
mode macro	does not place: MPL-0003, its edge pins need channels the floorplan does not have

On XSTile the order flips (entry 49: inlining +7.7 % against placed arrays). No shape dominates; it is a per-design choice. These numbers answer a review comment on The-OpenROAD-Project/OpenROAD#11669, where mode netlist's unplaced periphery was asked about.

[oharboe]

Closed as reference only; the branch stays.

Main carries the base of this work (1644583: OpenROAD 0010 at #11669's head, ORFS 0089/0091/0099 as ORFS #4651), and #1209 took everything else that stood on main alone. What this branch still held at its tip (7ee797b):

• Seams, ORFS patch 0093: a register file in place of a memory yosys infers inside a module, with asap7/tinyRocket-regfile and its seam_test. Nothing on main needs it today; pick it up from here when a design does.
• The ladder, test/regfile/ladder and ORFS 0095–0098, 0100, 0104, 0105: -regfile variants of picorv32, ibex, swerv, cva6 and riscv32i against their flip-flop arms at global route, plus simulation of each generated register file against the RTL module it replaces, which exercises 0010's async_reset, SystemVerilog ports, unused and write_priority on real cores. Its per-design rows were never recorded in the repository and are not reproduced here.
• The riscv32i campaign, test/regfile/campaign and ORFS 0101: results.md has the measurements. Riscv32i's register file reaches parity with flip-flops (955 ps against 954 ps, on less area) with a clock gate per word and no macro.

coralnpu lives in OpenROAD-flow-scripts#4653.

🤖 Generated with Claude Code