regfile: why a register file placed as a macro needs a bigger core (study)

MODULE.bazel

@@ -121,12 +121,64 @@ archive_override(
         # pull request carries a gtest. Retires at a bump onto an OpenROAD
         # that has it.
         "//patches:0004-openroad-dpl-window-supply.patch",
-        # 0010: generate_regfile in the ram module, a multi-port register
-        # file as placed standard cells, which AUTO_MEMORIES_REGFILES
-        # (ORFS patch 0089) runs. The net diff of upstream
-        # The-OpenROAD-Project/OpenROAD#11669; retires at a bump onto an
-        # OpenROAD that has it.
-        "//patches:0010-openroad-ram-generate-regfile.patch",
+        # 0011 to 0026: OpenROAD #11669's register-file generator carried
+        # onto generate_ram, as options on it, one patch per pull request
+        # to come; not upstreamed.
+        # 0011: generate_ram with more than one write port, each with its
+        # own decoder and data, the last port winning a word both write.
+        "//patches:0011-openroad-ram-multiple-write-ports.patch",
+        # 0012: generate_ram reads through AND-OR trees where the library
+        # has no tristate cell (asap7), or when asked; a QN-only storage
+        # flop taken there. On 0011 (OpenROAD #11669); not upstreamed.
+        "//patches:0012-openroad-ram-and-or-read.patch",
+        # 0013: generate_ram -zero_word, a word that reads 0 and drops its
+        # writes (a RISC-V x0). On 0012 (OpenROAD #11669); not upstreamed.
+        "//patches:0013-openroad-ram-zero-word.patch",
+        # 0014: generate_ram -reset_value, an asynchronous reset of every
+        # word, per bit cleared or preset. On 0013 (OpenROAD #11669); not
+        # upstreamed.
+        "//patches:0014-openroad-ram-reset.patch",
+        # 0015: generate_ram -banks, -bank_columns, -bank_order: words in
+        # banks, each word decoded whole. On 0014 (OpenROAD #11669); not
+        # upstreamed.
+        "//patches:0015-openroad-ram-banks.patch",
+        # 0016: generate_ram -rb_ports, read ports with an address and data
+        # per bank. On 0015 (OpenROAD #11669); not upstreamed.
+        "//patches:0016-openroad-ram-banked-read-ports.patch",
+        # 0017: generate_ram -read_latency 1, registered read addresses. On
+        # 0016 (OpenROAD #11669); not upstreamed.
+        "//patches:0017-openroad-ram-read-latency.patch",
+        # 0018: generate_ram -write_style mux, a hold mux per bit for the
+        # clock gate per word. On 0017 (OpenROAD #11669); not upstreamed.
+        "//patches:0018-openroad-ram-write-mux.patch",
+        # 0019: generate_ram_netlist -periphery unplaced, the core alone
+        # placed and outlined, for a parent to dissolve. On 0018 (OpenROAD
+        # #11669); not upstreamed.
+        "//patches:0019-openroad-ram-periphery-unplaced.patch",
+        # 0020: generate_ram -cells {role master ...} and -name. On 0019
+        # (OpenROAD #11669); not upstreamed.
+        "//patches:0020-openroad-ram-cells-name.patch",
+        # 0021: generate_ram -decoder word, a balanced AND2 tree per word.
+        # On 0020 (OpenROAD #11669); not upstreamed.
+        "//patches:0021-openroad-ram-word-decoder.patch",
+        # 0022: generate_ram -bit_folds, a word's slices in rows. On 0021
+        # (OpenROAD #11669); not upstreamed.
+        "//patches:0022-openroad-ram-bit-folds.patch",
+        # 0023: generate_ram_netlist -periphery verilog, the core a block of
+        # its own and its periphery a Verilog wrapper. On 0022 (OpenROAD
+        # #11669); not upstreamed.
+        "//patches:0023-openroad-ram-periphery-verilog.patch",
+        # 0024: generate_ram -write_priority or, ports writing one word in
+        # a cycle write the OR of their data. On 0023 (OpenROAD #11669);
+        # not upstreamed.
+        "//patches:0024-openroad-ram-write-priority-or.patch",
+        # 0025: generate_ram -service_columns, empty columns in the array
+        # for a parent's buffers. On 0024 (OpenROAD #11669); not upstreamed.
+        "//patches:0025-openroad-ram-service-columns.patch",
+        # 0026: generate_ram -bank_column_layout contiguous, a word's bits
+        # side by side in its row. On 0025 (OpenROAD #11669); not
+        # upstreamed.
+        "//patches:0026-openroad-ram-bank-column-layout.patch",
     ],
     strip_prefix = "OpenROAD-a3bf6124782f205ba5fa9e2e402dae8b665fc4fc",
     urls = ["https://github.com/The-OpenROAD-Project/OpenROAD/archive/a3bf6124782f205ba5fa9e2e402dae8b665fc4fc.tar.gz"],

config_mk_parser.py

@@ -65,7 +65,7 @@
     # before synthesis; run during canonicalization, so staged.
     "SYNTH_VERILOG_SURGERY",
     # AUTO_MEMORIES_REGFILES: register-file spec files gen_memories.py
-    # hands to OpenROAD's generate_regfile during canonicalization;
+    # translates to OpenROAD's generate_ram during canonicalization;
     # staged like the .memories files above.
     "AUTO_MEMORIES_REGFILES",
 }

ideas/tile-generator.md

@@ -0,0 +1,51 @@
+# A tile generator beside generate_ram
+
+An idea for later in the register-file campaign, not started. The user
+injects a repeating netlist, a tile, and a generic engine lays out the
+array of it: the tile's cells placed once by a solver (OR-tools CP-SAT),
+the array tiled by construction, the periphery built by hooks. It would
+sit *beside* generate_ram, not replace it. generate_ram covers storage
+with one word per row, decoders and read trees; the engine would cover
+the repeating structures generate_ram cannot express:
+
+- CAMs: a compare cell per bit, a match line per row reduced across it;
+- systolic and multiply-accumulate arrays: a 2-D tile wired to its
+  neighbours, no decoder;
+- FIFOs and shift or delay lines: a pointer ring as the periphery;
+- datapath bit-slices (adders, shifters, muxes): a bit per row, the
+  carry chain a net between neighbouring tiles.
+
+## What the user injects
+
+1. The tile netlist, of liberty cells, each port declared row-shared,
+   column-shared, wired to a neighbour (N, E, S, W) or periphery.
+2. Tiling rules: the tile's height in rows, its column pitch, mirroring
+   per row and column.
+3. Periphery hooks: a generator per row or column edge (decoder, driver,
+   reduction tree, pointer), each matched to the tile's pitch.
+4. Optionally, hints for the tile's solve: fixed cells, pin sides.
+
+Exact solvers handle tens to a few hundred objects, so CP-SAT fits the
+tile and the small choices around it (fold, aspect ratio, pin sides),
+not the array.
+
+## Prior art
+
+A literature search (2026-10-13) found the pieces but not the
+combination, and no published placement work that uses CP-SAT.
+
+- Injected cells, tiled: OpenRAM (https://github.com/VLSIDA/OpenRAM),
+  its bitcell and periphery modules overridable per technology; SRAM22
+  on Substrate, typed composable generators (Berkeley EECS-2023-137).
+  Both are custom-layout SRAMs only.
+- Standard-cell RAMs of fixed cells: DFFRAM, whose density came from a
+  placer that knew its structure (https://github.com/AUCOHL/DFFRAM);
+  OpenROAD's ram module, arXiv 2607.12244 (Louie, Nguyen, Liberty,
+  Rovinski).
+- Bit-slice alignment in a general placer: Ward et al., SAPT, IEEE
+  TCAD 32(2), 2013; regularity extraction, Chowdhary et al., ICCAD 1998.
+- Exact solvers for small layouts: SMTCell (UCSD), BonnCell (Bonn); ILP
+  detailed placement under array constraints in ALIGN, arXiv 2008.10682.
+
+Read first: arXiv 2607.12244, OpenRAM's override design with
+EECS-2023-137, then SAPT and ALIGN.

orfs_source.bzl

@@ -124,7 +124,7 @@ ORFS_PATCHES = [
     # //:bump onto an ORFS that carries it.
     Label("//patches:0094-orfs-synth-verilog-surgery.patch"),
     # 0089: AUTO_MEMORIES_REGFILES: register files listed by spec are
-    # built by OpenROAD's generate_regfile (OpenROAD patch 0010) as
+    # built by OpenROAD's generate_ram (OpenROAD patches 0011 to 0023) as
     # macros of placed standard cells; in `mode netlist` each dissolves
     # into its cells at the end of macro placement, its core FIRM where
     # the macro was placed, its address decode left to placement.
@@ -159,6 +159,15 @@ ORFS_PATCHES = [
     # for a fresh snapshot of coralnpu; and the coralnpu README. Needs
     # 0103.
     Label("//patches:0106-orfs-coralnpu-exmem.patch"),
+    # 0108: a register file with `periphery verilog` in mode netlist: its
+    # core the macro, <module>_core, and a wrapper of the periphery read
+    # in the module's place. On 0089 and 0091; retires with 0089. Not
+    # upstreamed.
+    Label("//patches:0108-orfs-regfile-periphery-verilog.patch"),
+    # 0109: register files through generate_ram (OpenROAD patches 0011 to
+    # 0023), a wrapper in the RTL module's place; every spec. On 0089, 0091 and 0108; retires
+    # with 0089. Not upstreamed.
+    Label("//patches:0109-orfs-regfiles-generate-ram.patch"),
 ]
 
 # Generate the BUILD file for any design directory that has a config.mk
@@ -333,6 +342,9 @@ exports_files(
 exports_files(
     [
         "scripts/flow.tcl",
+        # the register-file spec's translation to generate_ram (ORFS patch
+        # 0109), which test/regfile/cores runs on its own
+        "scripts/memories/regfile_ram.py",
         "scripts/synth.tcl",
         "scripts/variables.yaml",
     ],