regfile: why a register file placed as a macro needs a bigger core (study)

[oharboe]

Study for The-OpenROAD-Project/OpenROAD#11669: why riscv32i's register file placed as a macro needs a bigger core than the same cells inlined. Draft: the fixes come here one at a time, each measured before it moves to the OpenROAD PR or the ORFS patches.

test/regfile/riscv32i builds riscv32i's register file in each shape the generator offers (now generate_ram), on ORFS's own riscv32i config, beside ORFS's riscv32i (flip-flops). ledger.tcl accounts for every µm² of the core on any stage's ODB.

riscv32i, 62 %, global route, 950 ps clock. Minimum period from placement parasitics on the global-route ODB (about 5 ps off the route log's reading); the core is sized by utilization, so the channel width doesn't change it.

shape	core µm²	RTLMP_MIN_CHANNEL_SIZE 8 8 (riscv32i)	2 2 (*_narrow)
flops	4012	950 ps	992 ps
inlined	3544	944 ps	950 ps
inlined, periphery verilog	3516	938 ps	946 ps
netlist, 996 µm² abstract (macro-placed, then dissolved)	4319	953 ps	FLW-0004, placed partly outside the core
netlist, service_sites 0, 835 µm² abstract	4067	MPL-0003	939 ps
macro	4319	MPL-0003	PDN-0233
after the fixes: netlist, 673 µm² abstract + row halo, 62 %	3803	MPL-0003	MPL-0003
after the fixes: netlist, 55 %	4283		938 ps
netlist, periphery verilog, 55 %	4287		940 ps

At 55 % with the padded abstract, AutoMemories.md measured 959 ps on 4644 µm².

Left unset, ORFS uses 20 20 and every shape fails macro placement, flops included.

The register file's abstract is 53.5 × 18.6 µm = 996 µm² and holds 478 µm² of cells. The rest is a decode column mode netlist leaves to the parent (225 µm²), row ends and service columns (198 µm²) and tile slack (95 µm²). initialize_floorplan -utilization charges the whole abstract: 96 % of the 775 µm² larger core.

Steps

• The ledger and the four shapes, *_narrow beside them.
• service_sites 0, no code change: the abstract drops to 44.8 × 18.6 µm = 835 µm² and the core to 4067 µm², and macro placement fails with MPL-0003. riscv32i's RTLMP_MIN_CHANNEL_SIZE 8 8, sized for its FakeRAMs, puts the macros at 3279 µm² with channels against 2239 µm² without; the padded abstract was what gave the placer room. So the generator fix needs the ORFS side with it.
• RTLMP_MIN_CHANNEL_SIZE 2 2 on every shape (table). Narrow channels cost flops 42 ps, so the fix is a narrow channel for the register file only, not a global setting.
• OpenROAD, generate_regfile (patch 0010): in mode netlist the abstract is the placed core's bounding box plus one row for row parity, and no service columns by default: 996 → 673 µm², 48 % → 72 % cells.
• ORFS (patch 0089): each mode-netlist register file gets an instance halo of MACRO_ROWS_HALO_X/Y, so the rows cut around the FakeRAMs as it dissolves stay clear of its core (FLW-0014 without it; the padded outline hid this).
• At 62 % riscv32i's four 42 µm tall FakeRAMs and the 17 µm register file with its halo need 63 µm of a 61.6 µm core and do not tile; at 55 % it reaches global route at 938 ps on 4283 µm².
• Tests: OpenROAD's ram tests (generate_ram's 4 and a golden test per new option) run here as //test/regfile:openroad_ram_tests; the regfile tests read //test's asap7 files instead of a symlink bazel's patcher cannot create.
• periphery generator|verilog: who builds the periphery. verilog writes it as assigns for synthesis to map with the parent; an option, since which is better depends on the integration. Simulated against riscv32i's RTL.
• periphery verilog with mode netlist: the macro is the core alone, <module>_core, and a wrapper of the periphery is read in the module's place (ORFS patch 0108). Simulated against riscv32i's RTL.
• Port into generate_ram (Austin's generator), one patch per future PR:
  • 0011, more than one write port: a decoder, data, write enables and address per port, the last port winning a word two write. generate_ram's existing tests unchanged; a new golden test in its format; simulated against its behavioral model on Nangate45 (tristate bitlines), collisions included. lib_to_verilog learned tristate outputs and Nangate45's quoted flip-flops to make that simulation possible.
  • 0012, a read path without tristates: -read_style and_or, an AOI22/NAND2/NOR2 tree per bit column, the default where the library has no tristate cell (asap7). A flop whose output is its data inverted (asap7's DFFHQNx1) taken there; buildPortMap now counts next_state in a flop's polarity. Golden asap7 test in generate_ram's format; simulated in three shapes against the behavioral model.
  • 0013 -zero_word: a word that reads 0 and drops its writes.
  • 0014 -reset_value: asynchronous reset of every word, per bit cleared or preset by the flop's own polarity; polarity and synchronous reset adapted outside.
  • 0015 -banks, -bank_columns, -bank_order: each word decoded whole, so banks need not be powers of two (XiangShan's 224 words in 4 interleaved banks). Also gives every inverter column a port: arrays with fewer rows than address bits had no address inverters.
  • 0016 -rb_ports: banked read ports, an address and data per bank.
  • 0017 -read_latency 1: registered read addresses.
  • 0018 -write_style mux: a hold mux per bit instead of a clock gate per word.
  • 0019 -periphery unplaced: the core alone placed and outlined, pins on a layer's tracks where their nets land (generate_regfile's mode netlist).
  • Each with a golden test in generate_ram's format; test/regfile/sim simulates 24 shapes of netlist against generate_ram's behavioral model on Nangate45 and asap7, 20 000 cycles each, no mismatch. generate_ram's own tests unchanged.
  • 0020 -cells {role master} and -name: cells by role (the smallest asap7 cells are the dont_use xp ones and the hold buffer), blocks named per module. findMaster4 now reads the pins of the cell it picks.
  • 0021 -decoder word: a balanced AND2 tree per word; the row decoder's AND2 chain was 60 ps of riscv32i's 220 ps read path.
  • 0022 -bit_folds k: a word in k rows, its write logic shared by its folds; XiangShan's IntRegFile (12 reads, 9 writes) went from 1458 x 31 um to square.
  • 0023 -periphery verilog: the core a block of its own, the periphery a Verilog wrapper.
  • 0024 -write_priority or: ports writing one word in a cycle write the OR of their data, as firtool's register files describe it (generate_regfile's default); the mux-write equivalence checks against XiangShan's RTL failed without it.
  • 0022, amended: -bit_folds with a short last fold (FtqMetaQueueRedirect, 211 bits in 4; FtqMetaQueueResolve, 954 in 8).
  • 0025 -service_columns {every sites}: empty columns in the array for a parent's buffers, generate_regfile's tap_columns/service_sites.
  • 0026 -bank_column_layout contiguous: a row's words side by side instead of interleaved bit by bit (below).
• ORFS 0109: AUTO_MEMORIES_REGFILES through generate_ram: memories/regfile_ram.py translates a spec to generate_ram_netlist options and writes a wrapper in the RTL module's place (ports from the yosys JSON, reset polarity adapted there); flops renamed to store_name/read_reg_name. Every spec translates, kept macros included (pins placed, a power grid with VDD/VSS pins, a timing model with its area).

riscv32i through generate_ram (global route, placement parasitics, 950 ps clock):

shape	generator	core µm²	min period
inlined, 62 %	generate_regfile	3544	944 ps
inlined, 62 %	generate_ram	3503	943 ps
netlist, 55 %, 2 µm channels	generate_regfile	4283	938 ps
netlist, 55 %, 2 µm channels	generate_ram	3968	945 ps
netlist, 62 %, 2 µm channels	generate_ram	3512	939 ps

The macro-placed shape now fits riscv32i's own 62 % and matches the inlined one: the dissolved core is 55.3 × 8.6 µm and 93 % cells, where generate_regfile's padded abstract was 48 %.

• ORFS onto generate_ram, 0010 dropped: the equivalence checks (test/structured_gen_lec, all 21 pass), structured_gen's golden test, the planner, the scaffolds and the planned parent's probes find generate_ram's RAM in the wrapper.

• XiangShan's register files at real size in a parent (test/structured_netlist, through CTS). Tight outlines exposed what generate_regfile's half-empty tiles had hidden: a word's selects and write enables are as long as its bits are spread, and a parent buffers them inside a full array, where nothing legalizes.

  	a word spans	parent at place
  RobEntryFile, 4 words a row interleaved	278 µm	6,483 slew violations, fails
  RobEntryFile, contiguous (0026)	74 µm	608, passes
  RenameBufferFile, a word a row	258 µm	fails
  RenameBufferFile, folded in 2	129 µm	passes
  IntRegFile, 2 words a row, 8 folds	96 µm	passes

  regfile_ram.py lays out a row's words contiguous by default and folds a word whose bits would span more than 150 µm. The scaffold's ring holds the periphery generate_ram leaves to the parent (7,027 µm², 82,040 cells for RenameBufferFile: a balanced decode per word and port).

• The reply to Austin on OpenROAD#11669 (the planned PRs, each with its use case), and #11669 closed in favour of them.

• The breakout: 16 single-concern OpenROAD PRs and the ORFS ones; the usage text and README of the ram module tidied first.

• ORFS: the floorplan sized by the register file's cell area. On riscv32i this makes the core smaller, which the FakeRAMs already do not fit; to measure on XiangShan.

• Macro mode's MPL-0003: later, with RTL MP placing banks of memories on XiangShan.

Every target is manual. To reproduce:

bazelisk build //test/regfile/riscv32i:riscv_top_netlist_grt
bazelisk run //test/regfile/riscv32i:netlist_floorplan_odb_debug

🤖 Generated with Claude Code

[oharboe]

Superseded by #1234, which carries everything from this study.