Repository navigation
regfile: register files through generate_ram, carried until upstream - #1234
Merged
Merged
Conversation
Carries everything register files need, so the flow can use them while the upstream changes are reviewed: - OpenROAD patches 0011 to 0026: generate_ram's register-file options, one patch per concern (multiple write ports, AND-OR read, zero word, reset, banks, banked read ports, read latency, write mux, unplaced and Verilog periphery, cells and name, word decoder, bit folds, write priority, service columns, bank column layout). Each carries a golden test in OpenROAD's ram test format. - ORFS patch 0089: AUTO_MEMORIES_REGFILES through generate_ram, a spec translated by memories/regfile_ram.py, a wrapper in the RTL module's place, inlined or macro-placed and dissolved. 0091, 0099, 0107 and their generate_regfile predecessor are folded into it. - The integration tests: test/regfile (generate_ram's tests, netlists simulated against its behavioral model, ibex and riscv32i against their RTL), test/structured_gen_lec (equivalence against firtool's register files), XiangShan's register files at real size in a parent through CTS (test/structured_netlist), the planned parent. Each patch retires at a //:bump onto an upstream that carries it. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
This was referenced Oct 13, 2026
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Register files of placed standard cells through OpenROAD's
generate_ram, carried here until upstream has them, so ORFS designs can use them now. This is the integration test for the upstream changes, and it will be extended to XiangShan.Carried
generate_ram's register-file options, one patch per concern, each with a golden test in OpenROAD'sramtest format. They go upstream as one OpenROAD PR with one commit per concern.AUTO_MEMORIES_REGFILESthroughgenerate_ram.memories/regfile_ram.pytranslates a spec intogenerate_ramoptions, checks it against the module's ports, and puts a wrapper in the module's place. The register file is inlined, or macro-placed and dissolved. It goes upstream as ORFS #4651.Integration tests
test/regfile:generate_ram's tests; netlists simulated against its behavioral model on Nangate45 and asap7; ibex's and riscv32i's register files simulated against their RTL; riscv32i through global route.test/structured_gen_lec: equivalence against firtool's register files, at small sizes.test/structured_netlist: XiangShan's RobEntryFile, RenameBufferFile and IntRegFile at real size, in a parent, through CTS.test/planned_parentandtools/structured_gen: the planner and the views.riscv32i with its register file inlined reaches 943 ps on a 3,503 um2 core, against 950 ps on 4,012 um2 with flops.
Each patch retires at a
//:bumponto an upstream that carries it. Supersedes the study in #1221.🤖 Generated with Claude Code