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Special verilog parameters tb_path and output_path don't work in Riviera-PRO #683

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Special verilog parameters tb_path and output_path don't work in Riviera-PRO #683

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8 changes: 5 additions & 3 deletions vunit/sim_if/rivierapro.py
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Original file line number Diff line number Diff line change
Expand Up @@ -279,7 +279,8 @@ def _create_load_function(self, test_suite_name, config, output_path): # pylint
Create the vunit_load TCL function that runs the vsim command and loads the design
"""
set_generic_str = " ".join(
(f"-g/{config.entity_name!s}/{name!s}={format_generic(value)!s}" for name, value in config.generics.items())
f"-g/{config.entity_name!s}/{name!s}={format_generic(name, value)!s}"
for name, value in config.generics.items()
)
pli_str = " ".join(f'-pli "{fix_path(name)}"' for name in config.sim_options.get("pli", []))

Expand Down Expand Up @@ -424,12 +425,13 @@ def merge_coverage(self, file_name, args=None):
print("Done merging coverage files")


def format_generic(value):
def format_generic(name, value):
"""
Generic values with space in them need to be quoted
We know that tb_path and output_path are strings - they also need to be in quote
"""
value_str = str(value)
return f'"{value_str!s}"' if " " in value_str else value_str
return f'"{value_str!s}"' if " " in value_str or name == "output_path" or name == "tb_path" else value_str


class VersionConsumer(object):
Expand Down