Add support for Metrics simulator (DSim) to Vunit#756
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aimeepsutton wants to merge 2 commits intoVUnit:masterfrom
Open
Add support for Metrics simulator (DSim) to Vunit#756aimeepsutton wants to merge 2 commits intoVUnit:masterfrom
aimeepsutton wants to merge 2 commits intoVUnit:masterfrom
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Hi @aimeepsutton. Great to see your progress. Please, provide me with access and I will test this. |
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Hello Lars and Vunit maintainers, this pull request adds support for the Metrics simulator (DSim) to Vunit. So far only Verilog and SystemVerilog designs can be simulated with Metrics, however we are actively developing VHDL simulation capabilities. Once our VHDL support is sufficient, we will make another pull request to update the Metrics interface to Vunit accordingly.
Please contact me with any questions. I can provide you with access to the Metrics simulator for testing purposes.