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(Re)move AXI and UART verification components to separate repos

Verification Components

Status: Draft (not ready).

VUnit/vunitnumber 511

#511 In VUnit/vunit;

· eine opened on Jun 4, 2019

Add compliance tests and updated VCs accordingly

Verification Components

Status: Open (in progress).

VUnit/vunitnumber 520

#520 In VUnit/vunit;

· LarsAsplund opened on Jun 17, 2019

vci: refactor

Status: Open (in progress).

VUnit/vunitnumber 759

#759 In VUnit/vunit;

· umarcor opened on Oct 22, 2021

Tweaks to the Builtins API

Builtins

Status: Open.

#765 In VUnit/vunit;

· umarcor opened on Oct 23, 2021

Extend <code>dict_t</code> to handle any type

Enhancement

Status: Open.

#830 In VUnit/vunit;

· LarsAsplund opened on May 14, 2022

write_bus(...) doesn't check if write address is inside address range of the bus

Enhancement

Status: Open.

#879 In VUnit/vunit;

· creiter64 opened on Dec 1, 2022

loghandler log level issue

Bug

Docs

Status: Open.

#890 In VUnit/vunit;

· sjoerss opened on Jan 17, 2023

Special verilog parameters tb_path and output_path don't work in Riviera-PRO

Needs testing

Simulator support

SystemVerilog

Status: Open (in progress).

VUnit/vunitnumber 683

#683 In VUnit/vunit;

· pib88 opened on Sep 29, 2020

Xcelium support

Simulator support

Status: Open (in progress).

VUnit/vunitnumber 684

#684 In VUnit/vunit;

· powARman opened on Sep 29, 2020

No opportunity to append sim_option in test_case

Enhancement

Status: Open.

#687 In VUnit/vunit;

· arnfol opened on Oct 21, 2020

Allow simulator interfaces to accept an environment argument

Enhancement

Simulator support

ThirdParty: cocotbRelated to cocotb.Related to cocotb.

Status: Open.

#708 In VUnit/vunit;

· jwprice100 opened on Feb 16, 2021

Add Cadence Xcelium support

Simulator support

Status: Draft (not ready).

VUnit/vunitnumber 728

#728 In VUnit/vunit;

· rodrigomelo9 opened on Aug 29, 2021

Update to activehdl.py required for VHDL-2019 support

Simulator support

Status: Open.

#755 In VUnit/vunit;

· Andy-Darlington opened on Oct 14, 2021

Add support for Metrics simulator (DSim) to Vunit

Enhancement

Simulator support

SystemVerilog

Status: Open (in progress).

VUnit/vunitnumber 756

#756 In VUnit/vunit;

· aimeepsutton opened on Oct 21, 2021

Building VUnit's verification components and OSVVMLibraries at the same time

Builtins

ThirdParty: OSVVMRelated to OSVVM and/or OSVVMLibraries.Related to OSVVM and/or OSVVMLibraries.

Status: Open.

#767 In VUnit/vunit;

· umarcor opened on Oct 24, 2021

Support hierarchical library mapping in ModelSim

Enhancement

Tool: Questa

Status: Open (in progress).

VUnit/vunitnumber 775

#775 In VUnit/vunit;

· ThomasWismer opened on Oct 30, 2021

Add configuration support

Enhancement

ThirdParty: OSVVMRelated to OSVVM and/or OSVVMLibraries.Related to OSVVM and/or OSVVMLibraries.

Status: Open (in progress).

VUnit/vunitnumber 785

#785 In VUnit/vunit;

· LarsAsplund opened on Jan 1, 2022

Add feature to select simulator programatically

Enhancement

Simulator support

Status: Open (in progress).

VUnit/vunitnumber 805

#805 In VUnit/vunit;

· nfrancque opened on Mar 6, 2022

Detect dual test case run

Builtins

Enhancement

Status: Open (in progress).

VUnit/vunitnumber 824

#824 In VUnit/vunit;

· std-max opened on May 10, 2022

Improving regexs that scan attributes

Enhancement

Status: Open (in progress).

VUnit/vunitnumber 836

#836 In VUnit/vunit;

· std-max opened on May 31, 2022

proposal for vhdl_parser to fix the issue #808

Enhancement

Parsing

Status: Open (in progress).

VUnit/vunitnumber 839

#839 In VUnit/vunit;

· asicnet opened on Jun 1, 2022

Fix some Vivado issues (SystemVerilog support, space in file name, environment variable)

Docs

Enhancement

Simulator support

Status: Open (in progress).

VUnit/vunitnumber 871

#871 In VUnit/vunit;

· oscargus opened on Nov 7, 2022

Improved changelog to be automatically managed by towncrier

CI

Docs

Enhancement

Status: Open (in progress).

VUnit/vunitnumber 885

#885 In VUnit/vunit;

· GlenNicholls opened on Jan 6, 2023

Parity bit in the uart VCs

Enhancement

Verification Components

Status: Open (in progress).

VUnit/vunitnumber 906

#906 In VUnit/vunit;

· nicdes opened on Feb 26, 2023

Move project metadata to pyproject.toml

Enhancement

Status: Open (in progress).

VUnit/vunitnumber 942

#942 In VUnit/vunit;

· lavovaLampa opened on Jul 7, 2023