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Feature/ram architecture dive - #18

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Feature/ram architecture dive#18
CL-BAF wants to merge 8 commits into
Yoosseph:mainfrom
CL-BAF:feature/ram-architecture-dive

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@CL-BAF

@CL-BAF CL-BAF commented Sep 20, 2026 •
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Closes #5

Summary

  • add a four-stage RAM architecture dive from the existing motherboard memory modules through DIMM, DRAM package, bank organisation, and individual bank structure
  • add a representative DDR5 UDIMM model with eight x8 DRAM packages, PMIC, SPD hub, keyed PCB geometry, and 288 edge contacts
  • add a DRAM package view with substrate, die, and BGA connections while keeping package internals explicitly illustrative
  • add a logical DDR5 die view with 8 bank groups × 4 banks for the represented 16 Gbit x8 organisation
  • add a bank-level diagram covering rows, columns/bitlines, sense amplifiers / row buffer, and 1T1C memory cells
  • distinguish physical DIMM/package views from logical bank/cell diagrams so the visualisation does not imply a literal die floorplan
  • integrate the new Memory branch with the existing scale, concept, search, navigation, and model-registration systems
  • preserve the existing motherboard RAM geometry, DIMM-slot behaviour, search behaviour, and DDR5 key-notch handling
  • add RAM-specific technical sources and update the project reference documentation
  • add dedicated regression and architecture tests for the new memory hierarchy

Automated verification

  • npm run check
  • npm run lint
  • npm test — 61/61 passing
  • npm run build
  • git diff --check

Browser QA

  • full motherboard → DIMM → DRAM package → banks → bank drill-down
  • breadcrumb/back navigation through the full Memory branch
  • existing RAM search and selection behaviour
  • DIMM explode/disassembly behaviour
  • desktop rendering and interaction
  • mobile rendering and navigation
  • no application console errors during the tested flow

Ready for maintainer review. The Vercel status remains an external deployment-authorization failure; CI/CD is maintainer-owned and was intentionally left unchanged.

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@Yoosseph

Yoosseph commented Sep 20, 2026 •
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As discussed on Discord, before the final review you'll:

  • clean up and refactor the implementation where needed, especially the AI-assisted parts
  • make sure the code is understandable and that you know what the generated code is doing
  • further polish the RAM visuals so they better match the quality of the other components
  • make the DIMM look more like a recognizable consumer module, using something Kingston/Corsair-inspired as a visual reference

Once that's done comment here in the thread and I'll take another look and review the PR.

@Yoosseph Yoosseph mentioned this pull request Sep 27, 2026
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Yoosseph added a commit that referenced this pull request Sep 27, 2026
@Yoosseph @CL-BAF
Rebuild the memory dive and add DDR4 beside it (#27)
00d2784 
* Add a DDR5 memory dive (PR #18, rebased onto main)

Squashes the eight commits of pull request 18 onto the current main:
module, package, bank array and bank scales, with sources and tests.

* Rebuild the memory dive and add DDR4 beside it

The module, package and diagrams from #18 were rebuilt against data sheets:

- Module: one extruded board outline with a real key, latch notches and,
  on DDR4, the curved contact edge; 288 contacts at the JEDEC 0.85 mm
  pitch; the published height and thickness with the spreader; PMIC,
  inductors and SPD hub on DDR5, SPD EEPROM and fly-by termination on
  DDR4; separate front and back plates with locking clips and pads.
- Package: the board-on-chip FBGA both generations use, die face down
  over a slot in the substrate, centre pads, bond wires, encapsulant
  and the 78-ball 13 x (3 + 3) grid it leaves room for.
- Die: bank groups with their own I/O, 32 banks (DDR5) or 16 (DDR4),
  and the centre-stripe periphery: command, mode registers, refresh,
  on-die ECC or DLL, prefetch, data I/O and ZQ.
- Bank: mats, local sense-amplifier stripes, sub-wordline drivers,
  global wordlines and bitlines, decoders and bank control.
- New cell scale: wordlines, bitlines, access transistors, charged and
  empty capacitors under the plate, precharge, sense amplifiers, column
  select and local I/O.

The DDR4 module (FURY Beast DDR4-3200) sits beside the installed DDR5
one in the Memory menu, each in its own dropdown, and the pair forms a
Memory group in the comparison workbench. The motherboard now carries
the complete DDR5 model in its slots, keyed from the module's own key.

* Take DDR4 down to the bank and the cell, and clean up the spreader

DDR4 now dives as deep as DDR5. Its bank and cell scales are the DDR5 ones
under ddr4 ids with the numbers that differ swapped in: a 17-bit row
address and 131,072 rows per bank, 64 bits per column access, and
wordlines boosted to 2.5 V instead of 1.8 V. The comparison sheet gains a
Bank and cell row saying the same.

The spreader and pads no longer flicker as the camera moves. The
interlock and the pads shared faces with the plates and with each other;
they now stop short of them. The locking clips sit inside the plates'
outline instead of standing off the edge as tabs, the wordmark is printed
on the plate rather than floating at ridge height, and the back tape
fills the gap to the laminate and leaves downward with the back plate
instead of rising through the board.

---------

Co-authored-by: cameron lonnie <goone499@gmail.com>
@Yoosseph

Yoosseph commented Oct 13, 2026

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Thanks @CL-BAF. This work is now on main and live on pc-anatomy.com. #27 squashed your eight commits onto current main with you credited as co-author, then rebuilt the module, package and diagrams against data sheets (Kingston FURY Beast-based DIMM, board-on-chip FBGA, die, bank and cell) and added DDR4 alongside DDR5. Since everything here is already in main, I'm closing this one in favour of #27. Your groundwork made it possible.

@Yoosseph Yoosseph closed this Oct 13, 2026

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RAM architecture dive

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@CL-BAF @Yoosseph