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Rebuild the memory dive and add DDR4 beside it - #27

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Yoosseph merged 3 commits into
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ram-dive
Sep 27, 2026
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Yoosseph merged 3 commits into
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ram-dive

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Closes #5. Supersedes #18: its commits are included here, squashed and rebased onto main with @CL-BAF kept as author.

DDR5 (Kingston FURY Beast DDR5-6000 16 GB, installed) and DDR4 (FURY Beast DDR4-3200 16 GB, alternative), each diving module → package → die → bank → cell, each in its own dropdown under Memory.

  • Module: one extruded board outline with a real key, latch notches and DDR4's curved contact edge; 288 contacts at the JEDEC 0.85 mm pitch; the data sheets' height and thickness with the spreader. PMIC, inductors and SPD hub on DDR5; SPD EEPROM and fly-by termination on DDR4. Separate front and back plates, pads and tape, with no coplanar faces left to flicker.
  • Package: the board-on-chip 78-ball FBGA both generations use — die face down over a slot, centre pads, bond wires, encapsulant, and the 13 × (3 + 3) ball grid that leaves room for it.
  • Die: bank groups with their own I/O; 32 banks (DDR5) or 16 (DDR4); centre-stripe periphery with on-die ECC on DDR5 and a DLL on DDR4.
  • Bank and cell: mats, sense-amplifier stripes, decoders and global lines; the 1T1C cell with charged and empty capacitors. DDR4's are DDR5's with its own row count and 2.5 V wordline supply.
  • Motherboard: the slots now carry the complete DDR5 model, keyed from the module's own key.
  • Comparison: a Memory modules group with 12 catalogue-backed rows.

38 scales, 421 concepts, 73 sources. tsc, 84 tests, lint, format and build pass; every new scale was rendered and checked in a headless browser. ARCHITECTURE.md, README.md, SOURCES.md and the reference index are updated.

CL-BAF and others added 3 commits September 27, 2026 20:11
Squashes the eight commits of pull request 18 onto the current main:
module, package, bank array and bank scales, with sources and tests.
The module, package and diagrams from #18 were rebuilt against data sheets:

- Module: one extruded board outline with a real key, latch notches and,
  on DDR4, the curved contact edge; 288 contacts at the JEDEC 0.85 mm
  pitch; the published height and thickness with the spreader; PMIC,
  inductors and SPD hub on DDR5, SPD EEPROM and fly-by termination on
  DDR4; separate front and back plates with locking clips and pads.
- Package: the board-on-chip FBGA both generations use, die face down
  over a slot in the substrate, centre pads, bond wires, encapsulant
  and the 78-ball 13 x (3 + 3) grid it leaves room for.
- Die: bank groups with their own I/O, 32 banks (DDR5) or 16 (DDR4),
  and the centre-stripe periphery: command, mode registers, refresh,
  on-die ECC or DLL, prefetch, data I/O and ZQ.
- Bank: mats, local sense-amplifier stripes, sub-wordline drivers,
  global wordlines and bitlines, decoders and bank control.
- New cell scale: wordlines, bitlines, access transistors, charged and
  empty capacitors under the plate, precharge, sense amplifiers, column
  select and local I/O.

The DDR4 module (FURY Beast DDR4-3200) sits beside the installed DDR5
one in the Memory menu, each in its own dropdown, and the pair forms a
Memory group in the comparison workbench. The motherboard now carries
the complete DDR5 model in its slots, keyed from the module's own key.
DDR4 now dives as deep as DDR5. Its bank and cell scales are the DDR5 ones
under ddr4 ids with the numbers that differ swapped in: a 17-bit row
address and 131,072 rows per bank, 64 bits per column access, and
wordlines boosted to 2.5 V instead of 1.8 V. The comparison sheet gains a
Bank and cell row saying the same.

The spreader and pads no longer flicker as the camera moves. The
interlock and the pads shared faces with the plates and with each other;
they now stop short of them. The locking clips sit inside the plates'
outline instead of standing off the edge as tabs, the wordmark is printed
on the plate rather than floating at ridge height, and the back tape
fills the gap to the laminate and leaves downward with the back plate
instead of rising through the board.
@vercel

vercel Bot commented Sep 27, 2026

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Project Deployment Actions Updated
pc-anatomy Ready Ready Preview Sep 27, 2026 11:17pm UTC

@Yoosseph
Yoosseph merged commit 00d2784 into main Sep 27, 2026
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@Yoosseph
Yoosseph deleted the ram-dive branch October 13, 2026 14:44

This branch was previously deployed

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Preview — a904b1a2 Deployed Sep 27, 2026 by vercel[bot]
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RAM architecture dive

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