Pitfalls

Popular hardware description languages like VHDL, Verilog and SystemVerilog have certain drawbacks and pitfalls that should be avoided in Flutsch. This page is a collection of the problems identified in those languages.

SystemVerilog

Large Number of Keywords

SystemVerilog in particular has hundreds of keywords. Most designers (including me) don't even know what most of those keywords mean. Similarly, most tools only implement a small subset of all keywords which makes it difficult for a designer to judge if a keyword is safe to use.

For the sanity of all people involved, the number of keywords should be kept small.

Weak Type System

A weak type system is a big drawback in HDL as problems may only surface very late in the simulation or synthesis flow.

Dependency on 32-bit

In Verilog and SystemVerilog there are a lot of implicit dependencies on 32-bit integer values. Those dependencies are a legacy of software programming languages and make no sense in hardware, as integers can have any width.

Packed and unpacked array dimensions

The concept of packed and unpacked arrays makes no sense in hardware and is a pure software simulation construct. As it has no impact on the synthesized hardware, it should not matter for a designer what dimension he or she chooses.

Cluttering the Global Namespace

In Verilog everything is by default in the global namespace which leads to frequent name clashes. Libraries are an attempt to solve this issue, but they are cumbersome and difficult to use