Ports

Ports are the interface between a module, its sub-modules and its parent.

Signals that are part of a port-list have an explicit clock and/or reset. Signals with neither clock nor reset can also be given, they are by definition asynchronous to all other signals in the current module.

Signals not belonging to the same clock and reset group can not be used together in any expression/process block. This prevents clock-domain-crossing issues. To write clock-domain-crossing blocks/synchronizers in FLUTSCH, use the unsafe { /* ... */} keyword to disable those checks.

A possible syntax for port-lists may look something like this (ok, I don't like this too much... no better idea at the moment, though):

module A
  (
    {
      clk : clock,
      rst : reset,
      data : logic,
      ready : logic,
      ready : logic,
    },
  );

If no clock and/or reset is given, it is inferred from the parent module, if possible. If it is not possible, a compile time error will be thrown.