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1. cifar10-cnn_accelerator cifar10-cnn_accelerator Public

   CNN accelerator for CIFAR-10 on Zybo Z7-10 FPGA. System modeling in SystemC, RTL design in VHDL, functional verification with UVM, and Linux driver development.

   C 4

2. FIR_Filter_NMR_Spares FIR_Filter_NMR_Spares Public

   Implementation of N-Modular Redundancy with Spare Units (NMR) for a FIR filter to enhance fault tolerance and system reliability. The project uses redundant functional units, a voting mechanism for…

   VHDL

3. axi-stream-sorter axi-stream-sorter Public

   This repository contains an AXI-Stream sorting IP block written in Verilog. The design supports an AXI-Stream input and output interface, making it suitable for FPGA and ASIC-based sorting applicat…

   SystemVerilog

4. RISC-V_SV RISC-V_SV Public

   Implementation of basic RISCVI instrcution set in systemVerilog

   SystemVerilog