axi-stream-sorter

Overview

This repository contains an AXI-Stream-based sorting IP block implemented in Verilog. The IP receives data via an AXI-Stream input, sorts it using the Bubble Sort algorithm, and outputs the sorted data through an AXI-Stream output.

The design has been formally verified using SystemVerilog Assertions (SVA) and JasperGold to ensure correctness and reliability.

Features

• AXI-Stream Input/Output: Compatible with standard AXI-Stream interfaces.
• High-Throughput: Processes two 16-bit numbers per clock cycle.
• Optimized Sorting: Implements Bubble Sort for stable sorting.
• Formal Verification: Uses JasperGold to verify correctness.
• Verilog Implementation: Designed for FPGA/ASIC applications.

System Architecture

• Input: Receives two 16-bit numbers per clock cycle via AXI-Stream.
• Sorting Logic: Implements Bubble Sort algorithm.
• Output: Emits sorted numbers as quickly as possible via AXI-Stream.
  

Implementation Details

• Language: Verilog
• Sorting Algorithm: Bubble Sort
• Verification: SystemVerilog Assertions (SVA) with JasperGold
• Clock Cycle Behavior:
  • Every clock cycle, two numbers are received.
  • Sorted results are emitted as soon as possible.