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fix: Add fpga_top wrapper to solve I/O pin overutilization RISC-V Safety BIST CI #12: Commit b386714 pushed by gitBeraTB
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feat: Add Vivado Synthesis & Implementation version RISC-V Safety BIST CI #11: Commit 03298cd pushed by gitBeraTB
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fix: remove all skipped tests — 42/42 PASS, 0 SKIP RISC-V Safety BIST CI #10: Commit f279827 pushed by gitBeraTB
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fix(ci): consolidate workflows, fix Verilator lint warnings and Makef… RISC-V Safety BIST CI #9: Commit 6760c8b pushed by gitBeraTB
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feat: comprehensive cocotb testbench + GitHub Actions CI RISC-V Safety BIST CI #8: Commit 6d34fff pushed by gitBeraTB
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Merge branch 'main' of https://github.com/gitBeraTB/RISCV-Safety-BIST-IP RISC-V Safety BIST CI #7: Commit d09f3b3 pushed by gitBeraTB
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Update README.md RISC-V Safety BIST CI #6: Commit d1b94b4 pushed by gitBeraTB
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Update main.yml RISC-V Safety BIST CI #5: Commit 5f7a3d6 pushed by gitBeraTB
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Update main.yml RISC-V Safety BIST CI #4: Commit d8e17f3 pushed by gitBeraTB
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Verifying main.yml RISC-V Safety BIST CI #3: Commit 06fc0ee pushed by gitBeraTB
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Update workflow RISC-V Safety BIST CI #2: Commit 1be8484 pushed by gitBeraTB
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Create main.yml RISC-V Safety BIST CI #1: Commit c1dfa93 pushed by gitBeraTB
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