Pinned Loading
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RISCV-Safety-BIST-IP
RISCV-Safety-BIST-IP PublicISO 26262 Compliant Runtime BIST Controller for RISC-V Processors (SystemVerilog/UVM-Lite)
SystemVerilog 1
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Non-Stationary-Electron-Transport-Simulation
Non-Stationary-Electron-Transport-Simulation PublicMATLAB simulation of non-stationary electron transport using Boltzmann Transport Equations. Models Velocity Overshoot and Energy Relaxation for high-frequency (THz) semiconductor devices
MATLAB
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Async-FIFO-Formal-Verification
Async-FIFO-Formal-Verification Public"SystemVerilog Asynchronous FIFO implementation verified with Cocotb."
Python
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Scalable-Parametric-MAC-Accelerator-Tile-ASIC-Design-
Scalable-Parametric-MAC-Accelerator-Tile-ASIC-Design- PublicThis accelerator performs the fundamental matrix operation Y = W × X , where X is an input vector and W is a weight matrix.
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