Scalable Parametric MAC Accelerator Tile (ASIC Design)

Overview

This repository contains the complete RTL-to-GDSII implementation of a Parametric Matrix Multiplier-Accumulator (MAC) Accelerator Tile, designed for Neural Network inference acceleration. The design targets the XFAB 180nm technology node.

The accelerator performs the fundamental matrix operation $Y = W \times X$, where $X$ is an input vector and $W$ is a weight matrix. The architecture is soft-coded and parametric, allowing for scalable instantiation of MAC units. Two primary configurations were implemented and analyzed:

• Baseline (Single-MAC): Area-optimized configuration.
• Enhanced (Dual-MAC): Throughput-optimized configuration utilizing parallel processing units.

Architecture

The design is implemented in synthesizable Verilog HDL. It features a robust Finite State Machine (FSM) controlling the data flow and arithmetic operations.

Key Features

• Parametric Scalability: The NUM_MACS parameter controls the hardware generation, automatically adjusting internal logic, accumulators, and datapath routing.
• Fixed-Point Arithmetic:
  • Input/Weight: Q1.6 format (8-bit).
  • Accumulator: Q5.14 format (20-bit) to prevent overflow during intermediate calculations.
  • Output: Truncated back to Q1.6 format (8-bit) for system compatibility.
• FSM Control: Three-state controller (S_IDLE, S_PROCESS, S_DONE) managing memory access and compute cycles.
• Memory Management: Internal flatten/unpack logic handles vector mapping, enabling standard synthesis tools to process multi-dimensional matrix operations efficiently.

ASIC Design Flow

This project demonstrates a comprehensive industry-standard VLSI flow, with a strong emphasis on Cadence Electronic Design Automation (EDA) tools for the backend implementation.

1. Functional Verification

• Tool: Xilinx Vivado / ModelSim
• Methodology: A SystemVerilog self-checking testbench was used to verify the Device Under Test (DUT) against a Golden Model.
• Status: Both configurations passed verification with zero mismatches.

2. Logic Synthesis

• Tool: Cadence Genus
• Process: The generic RTL was mapped to the XFAB 180nm standard cell library.
• Constraints: Strict timing constraints were applied (Clock Period: 20ns / 50 MHz).
• Result: The tool successfully mapped complex arithmetic structures to technology-specific cells, meeting all setup and hold time requirements with positive slack.

3. Physical Implementation (Layout)

• Tool: Cadence Innovus
• Strategy: A flat layout strategy was employed to maximize optimization flexibility.
• Steps:
  • Floorplanning: Core utilization set to ~70% with standard power ring distribution.
  • Placement: Timing-driven placement optimization.
  • Clock Tree Synthesis (CTS): Balanced clock tree generation to minimize skew.
  • Routing: Signal routing with specific attention to DRC rules.
• Sign-off:
  • DRC (Design Rule Check): Manual fixes were applied for antenna violations using layer hopping and diode insertion.
  • LVS (Layout vs. Schematic): Verified netlist topology consistency.

Performance Results

The following data represents post-synthesis and implementation analysis for the target frequency of 50 MHz.

Metric	Single-MAC (Baseline)	Dual-MAC (Enhanced)	Improvement / Trade-off
Latency	32 Clock Cycles	16 Clock Cycles	2x Speedup
Total Area	14,510 um^2	18,658 um^2	~28% Area Increase
Total Power	1.38 mW	2.03 mW	47% Power Increase
Energy Efficiency	~44.2 Units	~32.5 Units	~26% More Efficient
Timing Slack	+5.285 ns	+5.724 ns	Timing Met

Note: While the Dual-MAC consumes higher instantaneous power, it completes the task in half the time, resulting in superior energy efficiency per task.

Repository Structure

├── rtl/
│   └── mac_tile.v             # Synthesizable Verilog Source Code
├── tb/
│   └── tb_mac_tile.sv         # SystemVerilog Testbench
├── scripts/
│   ├── genus_synth.tcl        # Cadence Genus Synthesis Script
│   └── innovus_impl.tcl       # Cadence Innovus Implementation Script
├── reports/
│   ├── timing/                # Genus Timing Reports
│   ├── power/                 # Genus Power Reports
│   └── area/                  # Genus Area Reports
└── docs/                      # Block diagrams and Layout views

## How to Run
Functional Simulation
The design can be simulated using any standard Verilog simulator (Vivado, Questa, Icarus).

Add mac_tile.v and tb_mac_tile.sv to the project.

Run behavioral simulation.

ASIC Flow
To reproduce the synthesis and layout results, access to the Cadence toolchain and the specific PDK (Process Design Kit) is required.

Synthesis: Run genus -f scripts/genus_synth.tcl

Implementation: Run innovus -files scripts/innovus_impl.tcl

Authors

Mehmet Baştürk
Yusuf Berat Bölükbaş