v0.1.5 – Initial SECDED RAM Release

Overview:
This release introduces a fully functional ECC-protected RAM module implemented in Verilog, featuring Single Error Correct, Double Error Detect (SECDED) support. It is suitable for FPGA simulation and synthesis as well as ASIC integration.

Key Features
-Configurable 8-bit or 16-bit data widths
-SECDED (Hamming ECC) for single-bit correction and double-bit detection
-Predefined, parameterizable RAM depth
-CPU-style interface via top-level FPGA wrapper (fpga_top.v)
-Simulation-ready testbenches:
-tb_ecc_ram.v – RAM module verification
-fpga_tb.v – FPGA wrapper simulation with error injection
-Simulation scripts for Icarus Verilog (run_iverilog.sh) and ModelSim (run_modelsim.do)
-Comprehensive documentation:
-ecc_algorithm.md – Hamming SECDED explanation
-memory_map.md – RAM layout and ECC bit assignments
-Fully synthesizable for FPGA or ASIC integration

Changes in this Release
-Initial implementation of ECC RAM core (ecc_ram.v)
-ECC encoding/decoding module (ecc_secded.v)
-FPGA top-level wrapper with CPU-style interface (fpga_top.v)
-Testbenches and simulation scripts for verifying ECC functionality
-Documentation for ECC algorithm and memory layout

Usage Notes:
-Supports automatic single-bit correction and double-bit error detection
-Configurable via parameters (DATA_WIDTH, RAM_DEPTH)
-Includes example scripts for quick simulation and waveform generation