Feature/idma#13
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- cleanup on how traces are enabled. Just TRACE variable. - Cleanup on configs and dependencies - optimisations that make simulation faster - 'cleantb' target for cleaning just the testbench - 'sim-fast' and 'sim-fast-uboot' easy targets for the fastest known config - make can be run with '-j N' to speedup testbench build - wrapper fix for .fst dump not working with Veril 5.049
- Xilinx CDMA only enabled in Xilinx build. - Enabling configs for enabling IDMA parts - Adding iDMA submodule (with custom patches).
- Master id width = 5
=> litedram RTL and includes regenerated
=> VGA wrapper
=> This probably breaks all Xilinx generated stuff
=> USB wrapper: fix parameter used (master instead of slave width)
- AXI side of AHB-AXI bridge signals added to u-boot (commented)
=> capture can be processed with ahb-axi capture analyzer tool
- Top file changes:
=> xbar: 2 new masters and 2 new slaves
=> master id width 5
=> For USB 64-bits path, the axi64_mmio_to_axilite32_v2 instance was
changed to axi_mmio_to_axilite32_v3 because of the id width change
=> CDMA: left there but axi64_mmio_to_axilite32_v2 changed to
axi_mmio_to_axilite32_v3 (id width)
=> iDMA Instantiation
=> UberDDR3 instantiation with updated parameters
- iDMA: using fork with small patches
- updated ahb-axi submodule
- DTS: updated DTS to use uncached region for descriptors. Needed for
memory coherency
- lots of debugging signals added (to be removed)
- Verilator infrastructure for iDMA (tested in u-boot). Needs to be
enabled manually.
Remark: tested only in RV32W64 config (with LiteDRAM). There is a
deadlock with UberDDR3 which needs to be solved.
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