P3-A1.3: connect smart SCL profiles to GUI and ESP32-P4 runtime

.github/workflows/smv-injector-gui.yml

@@ -4,17 +4,27 @@ on:
   push:
     paths:
       - 'apps/smv_injector_gui/**'
+      - 'tools/smv_profile_inspect.cpp'
+      - 'include/ariec61850/sampled_values/publisher_profile.hpp'
+      - 'include/ariec61850/scl/**'
+      - 'src/scl/**'
+      - 'tests/fixtures/scl/**'
       - '.github/workflows/smv-injector-gui.yml'
   pull_request:
     paths:
       - 'apps/smv_injector_gui/**'
+      - 'tools/smv_profile_inspect.cpp'
+      - 'include/ariec61850/sampled_values/publisher_profile.hpp'
+      - 'include/ariec61850/scl/**'
+      - 'src/scl/**'
+      - 'tests/fixtures/scl/**'
       - '.github/workflows/smv-injector-gui.yml'
 
 permissions:
   contents: read
 
 jobs:
-  static-smoke:
+  profile-bridge-smoke:
     runs-on: ubuntu-latest
     steps:
       - name: Checkout
@@ -26,28 +36,79 @@ jobs:
           node-version: '22'
 
       - name: JavaScript syntax
-        run: node --check apps/smv_injector_gui/app.js
+        run: |
+          node --check apps/smv_injector_gui/app.js
+          node --check apps/smv_injector_gui/scl_bridge_bootstrap.js
+          node --check apps/smv_injector_gui/profile_bridge.js
 
       - name: Required UI files
         shell: bash
         run: |
           test -s apps/smv_injector_gui/index.html
           test -s apps/smv_injector_gui/styles.css
+          test -s apps/smv_injector_gui/profile_bridge.css
           test -s apps/smv_injector_gui/app.js
+          test -s apps/smv_injector_gui/scl_bridge_bootstrap.js
+          test -s apps/smv_injector_gui/profile_bridge.js
+          test -s apps/smv_injector_gui/host_server.py
           test -s apps/smv_injector_gui/run.cmd
-          grep -q 'SMV Injector' apps/smv_injector_gui/index.html
           grep -q 'navigator.serial' apps/smv_injector_gui/app.js
+          grep -q '/api/scl/inspect' apps/smv_injector_gui/profile_bridge.js
+
+      - name: Build smart SCL profile engine
+        shell: bash
+        run: |
+          cmake -S apps/smv_injector_gui/host -B build-smv-gui -G Ninja -DCMAKE_BUILD_TYPE=Release
+          cmake --build build-smv-gui --target ariec61850_smv_profile_inspect
 
-      - name: Local-server smoke
+      - name: Profile compiler regression
         shell: bash
         run: |
-          python3 -m http.server 8765 --bind 127.0.0.1 --directory apps/smv_injector_gui >/tmp/smv-gui-http.log 2>&1 &
+          fixture=tests/fixtures/scl/sv-4800-structured-4i4v.scd
+          build-smv-gui/ariec61850_smv_profile_inspect "$fixture" > /tmp/profile-b.json
+          grep -q '"compatibilityClass":"B"' /tmp/profile-b.json
+          grep -q '"publisherRateHz":4800' /tmp/profile-b.json
+          build-smv-gui/ariec61850_smv_profile_inspect "$fixture" --counter-modulus 4800 > /tmp/profile-a.json
+          grep -q '"compatibilityClass":"A"' /tmp/profile-a.json
+          grep -q '"deviceSupport":"ready"' /tmp/profile-a.json
+
+      - name: Local backend smoke
+        shell: bash
+        run: |
+          python3 apps/smv_injector_gui/host_server.py --profile-tool build-smv-gui/ariec61850_smv_profile_inspect --port 8765 >/tmp/smv-gui-http.log 2>&1 &
           server_pid=$!
           trap 'kill ${server_pid} 2>/dev/null || true' EXIT
-          for attempt in $(seq 1 20); do
-            if curl --fail --silent http://127.0.0.1:8765/ >/tmp/smv-gui-index.html; then
-              break
-            fi
-            sleep 0.25
+          for attempt in $(seq 1 30); do
+            if curl --fail --silent http://127.0.0.1:8765/ >/tmp/smv-gui-index.html; then break; fi
+            sleep 0.2
           done
           grep -q 'ARStack61850' /tmp/smv-gui-index.html
+          curl --fail --silent -X POST \
+            -H 'X-File-Name: fixture.scd' \
+            --data-binary @tests/fixtures/scl/sv-4800-structured-4i4v.scd \
+            'http://127.0.0.1:8765/api/scl/inspect?counterModulus=4800' >/tmp/api.json
+          grep -q '"deviceSupport":"ready"' /tmp/api.json
+
+  windows-launcher-smoke:
+    runs-on: windows-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+
+      - name: Simulate locally deleted host scaffold
+        shell: powershell
+        run: Remove-Item 'apps\smv_injector_gui\host' -Recurse -Force
+
+      - name: Verify native-host launcher and self-heal
+        shell: cmd
+        run: apps\smv_injector_gui\run.cmd --build-only
+
+      - name: Verify Windows profile compiler
+        shell: powershell
+        run: |
+          $tool = Join-Path $PWD 'build-smv-gui\ariec61850_smv_profile_inspect.exe'
+          if (-not (Test-Path $tool)) { throw "profile compiler missing: $tool" }
+          & $tool 'tests\fixtures\scl\sv-4800-structured-4i4v.scd' '--counter-modulus' '4800' | Tee-Object -FilePath profile-a.json
+          if (-not (Select-String -Path profile-a.json -SimpleMatch '"deviceSupport":"ready"')) {
+            throw 'Windows profile compiler did not produce a deployable Class-A fixture result'
+          }

ESP32_EMBEDDED_ROADMAP.md

@@ -0,0 +1,165 @@
+# ARStack61850 Embedded Runtime Roadmap
+
+## Product direction
+
+ARStack61850 is a portable IEC 61850 instrumentation stack with two complementary deployment classes:
+
+1. **Host / engineering** — Windows and Linux tools for SCL engineering, live discovery, evidence, diagnostics, waveform/scenario configuration, capture integration, and interoperability workflows.
+2. **Embedded / realtime runtime** — bounded protocol execution on dedicated hardware for deterministic SV/GOOSE publication, capture, timing evidence, and future synchronized operation.
+
+The host is the engineering brain. Dedicated hardware is the realtime packet and timing authority.
+
+## Process-bus hardware principles
+
+The embedded process-bus path requires a real Ethernet Layer-2 interface. Wireless networking is not a substitute for canonical SV/GOOSE transmission.
+
+Reference platforms should provide, as applicable:
+
+- raw Ethernet frame transmission and reception;
+- deterministic interrupt/DMA behavior;
+- hardware-assisted timestamps where available;
+- sufficient RAM for bounded packet/profile/capture buffers;
+- a management/control path that does not become the sample-timing source;
+- electrical isolation appropriate to the intended laboratory or field role.
+
+Board-specific pin maps, commercial product identities, and marketing specifications do not belong in the public architecture roadmap. Platform adapters keep those details outside the protocol core.
+
+## Non-negotiable architecture rules
+
+### Embedded core
+
+The embedded core may contain wire codecs, immutable compiled profiles, bounded state machines, and realtime signal/runtime primitives, but it must not depend on:
+
+- desktop socket APIs;
+- filesystem or interactive CLI workflows;
+- full XML/SCL parsing;
+- PCAP/evidence report generation;
+- desktop UI frameworks;
+- host-only discovery and engineering workflows.
+
+Platform ownership is injected through small HAL/adaptor contracts. RTOS, MAC/PHY, DMA, timestamp, USB/management, and board details remain outside the IEC 61850 semantic core.
+
+### SCL/profile boundary
+
+XML and vendor-specific engineering-file dialect handling stay on the host:
+
+```text
+SCL / CID / SCD / IID
+        |
+        v
+smart tolerant host parser
+        |
+        v
+validated immutable profile
+        |
+        v
+embedded runtime
+```
+
+The host may normalize representation differences, preserve provenance, quarantine irrelevant extensions, and explain conflicts. Deployment remains fail-closed when mandatory wire semantics are unresolved.
+
+### Realtime boundary
+
+The realtime publisher must not parse XML, rebuild BER per sample, allocate on the hot path, or depend on Windows/Linux scheduling.
+
+Preferred execution model:
+
+```text
+validated profile + mutable signal state
+                |
+                v
+       prebuilt packet template
+                |
+                v
+        deterministic scheduler
+                |
+                v
+          Ethernet MAC/DMA
+                |
+                v
+          timing evidence
+```
+
+Signal values may change coherently while running. Stream identity/layout changes require STOP -> validate -> arm.
+
+### Memory discipline
+
+Steady-state publisher/subscriber paths should use:
+
+- preallocated or caller-owned buffers;
+- bounded capacities;
+- no per-frame heap allocation;
+- no unbounded queues;
+- explicit overflow/drop accounting;
+- fixed or bounded metadata structures;
+- predictable CPU ownership.
+
+Host convenience models may use dynamic containers at configuration time as long as they do not leak allocation requirements into the realtime path.
+
+## Timing truth hierarchy
+
+Timing claims should progress through increasingly authoritative evidence:
+
+1. sample deadline;
+2. realtime task wake;
+3. MAC transmit/receive hardware timestamp where supported;
+4. independent measurement-point timestamp.
+
+Host arrival time is useful diagnostic information but must not be treated as canonical wire timing evidence.
+
+## Synchronization direction
+
+A future synchronized runtime should separate:
+
+- wire protocol parsing;
+- passive synchronization monitoring;
+- applicable profile validation;
+- hardware clock access;
+- offset/delay estimation and servo;
+- lock / acquiring / holdover states;
+- sample-synchronization field policy;
+- timestamp evidence.
+
+Presence of synchronization traffic alone is never proof of lock.
+
+## Process-bus capture direction
+
+The receive side should converge on the same realtime/evidence core used by the publisher:
+
+- promiscuous raw receive;
+- hardware timestamps where available;
+- bounded capture rings;
+- sequence/gap/duplicate/out-of-order accounting;
+- SCL expected-vs-observed comparison;
+- waveform, RMS, frequency, and phasor reconstruction;
+- triggers with bounded pre/post capture;
+- evidence export handled by the host.
+
+## Hardware evolution
+
+The current single-port MCU-class reference platform is suitable for proving deterministic publication, receive instrumentation, control-plane separation, and timestamp architecture.
+
+A later precision platform should be specified from measured needs rather than assumptions. Potential requirements include:
+
+- multiple independent process-side physical paths;
+- separate management path;
+- copper and/or optical interfaces as required by deployment;
+- timestamping close to the measurement point;
+- disciplined oscillator/clock architecture;
+- external switching, tapping, or programmable logic only where measured throughput/timing requirements justify it.
+
+## Delivery order
+
+1. deterministic SV publisher foundation;
+2. hardware timing evidence;
+3. smart SCL-to-profile compiler;
+4. immutable device-profile deployment;
+5. live engineering-value control through the GUI;
+6. broad interoperability matrix and observed-wire resolver;
+7. synchronized clock/profile support;
+8. hardware-timestamped process-bus analyzer;
+9. precision multi-port hardware when evidence requires it.
+
+## Public repository rule
+
+Public project-owned content remains vendor-neutral. Research findings from commercial implementations may inform engineering principles privately, but public architecture should contain standards, generic engineering patterns, reproducible measurements, and project-owned evidence rather than competitor/product references or UI imitation.