[masarray]

Summary

Connect the operator GUI to the C++ IEC 61850 SCL profile engine and add the first bounded immutable-profile deployment bridge to the ESP32-P4 publisher.

This remains vendor-neutral. Engineering files are normalized by the C++ SCL engine; the browser does not duplicate IEC 61850 semantics.

Workflow

Import SCL / CID
  -> C++ SCL parser + SvPublisherProfile compiler
  -> select resolved SV stream
  -> surface Class A/B/C and normalization warnings
  -> explicitly validate unresolved sample-counter policy
  -> configure test scaling when SCL does not establish it
  -> Deploy to device while STOPPED
  -> immutable profile armed on ESP32-P4
  -> Start
  -> live I/U/phase/frequency/quality changes continue through the existing realtime signal state

Implemented

• converges the SCL interoperability profile foundation with the existing GUI branch;
• adds a focused host ariec61850_smv_profile_inspect tool using SclParser and SvPublisherProfileCompiler;
• adds a localhost-only Python bridge endpoint for SCL compilation; temporary engineering files are deleted after each request;
• GUI stream selector with compatibility class, MAC, APPID, rate, payload and device-support state;
• fail-closed sample-counter confirmation: a rate-sized candidate remains Class B until explicitly validated;
• explicit current/voltage test scaling controls instead of pretending generic SCL always contains physical scaling;
• bounded PROFILE transaction over the existing serial development transport;
• profile identity/layout changes are rejected while RUNNING;
• immutable embedded runtime profile for MAC, APPID, VLAN/PCP, svID, confRev, publisher rate, counter modulus and supported ASDU field-presence options;
• canonical packet template is rebuilt only at Start/profile arm, never per sample;
• publisher rate is runtime-driven;
• 1 MHz GPTimer uses dynamic one-shot rational scheduling, so 4800 fps is represented by the exact repeating 208/208/209 us schedule instead of rounding to 208 us;
• diagnostic mirror follows the active publisher rate/configuration revision but remains a separate diagnostic identity;
• smpSynch remains 0 because this work does not claim PTP synchronization;
• Windows launcher discovers installed native Visual Studio/MSVC by capability rather than product year and self-repairs the small local host scaffold when required;
• GUI CI builds the host profile compiler and verifies anonymous 4800 4I+4V Class-B -> explicit-counter Class-A progression plus localhost API smoke.

Current device support boundary

The first ESP32-P4 deployment bridge intentionally accepts the physically proven 4I+4V layout: 16 ordered leaves as INT32 value + Quality pairs, 64-byte payload, one ASDU, SmpPerSec, explicit counter modulus. Other structurally valid SCL profiles are still parsed and explained, but show unsupported-layout instead of being guessed into this firmware layout.

This is a staged interoperability expansion, not a claim that every IEC 61850 SV profile is already deployable.

Physical acceptance achieved

The end-to-end injector workflow has now been exercised on physical ESP32-P4 hardware using a real engineering-file-derived 4800 fps profile:

1. engineering file imported through the GUI;
2. C++ SCL engine resolved one SV stream;
3. sample-counter modulus was explicitly confirmed and profile reached Class A / device support ready;
4. profile deployed and became the armed runtime profile;
5. GUI showed SCL-derived identity/rate including APPID, svID, VLAN/PCP intent, confRev, 4800 fps and wrap 4800;
6. ESP32-P4 ran approximately 4800 samples/s;
7. retained device telemetry showed zero missed slots and zero canonical TX failures;
8. three-phase waveform remained visible through the diagnostic mirror;
9. the diagnostic mirror reflected the active 4800 rate and configuration revision while retaining its distinct debug identity.

This is sufficient to mark the SMV Injector functional phase complete for the current supported 4I+4V profile boundary.

Remaining validation boundary

The following are intentionally not claimed by this PR:

• trusted independent on-wire proof of the canonical multicast destination, APPID, svID and VLAN/PCP, because the current host USB-Ethernet capture path reliably exposes the untagged broadcast diagnostic mirror but not the canonical tagged multicast stream;
• universal engineering scaling from arbitrary SCL;
• arbitrary embedded DataSet/type layouts;
• hardware TX timestamp jitter statistics;
• PTP discipline / synchronized smpSynch;
• formal IEC 61850-9-2 / IEC 61869-9 / legacy-profile conformance;
• broad relay/subscriber interoperability matrix.

The preferred next validation node is an independent raw Ethernet analyzer, potentially a second ESP32-P4 in promiscuous/all-multicast mode with application-layer VLAN parsing, connected through a direct link, TAP, or VLAN-preserving switch mirror/SPAN path.

See docs/SMV_INJECTOR_STATUS.md for the completion boundary and next-phase architecture.