Feature/cvxif coprocessors

[ntribie-bosch]

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This PR contains 2 coprocessors examples, and a wrapper , developped as part of the TRISTAN project :

- a configurable CRC coprocessor , which performs the inner CRC bitwise computation loop using any polynomial

- a EXPonential coprocessor, which computes exp(-x) in fixed point Q0.31 , where is in Q5.26 (i.e x is in [0,32[ and exp(-x) in ]0,1[)

- a wrapper, which allows to connect several coprocessors to a single cvx-if

By default, the coprocessors are not instantiated. An example instantiation is given at cva6 level for each of them

[github-actions]

Remaining comments which cannot be posted as a review comment to avoid GitHub Rate Limit

verible-verilog-format

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L36-L37

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L48-L48

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L50-L51

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L68-L70

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L73-L74

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L77-L78

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L81-L81

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L83-L84

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L125-L125

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L129-L129

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/cv32a6_scratchpad_config_pkg.sv#L133-L133

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/riscv_pkg.sv#L783-L786

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_exp/rtl_v/include/riscv_pkg.sv#L922-L922

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/cvxif_coprocessor_wrapper.sv#L16-L16

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/cvxif_coprocessor_wrapper.sv#L65-L65

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L14-L18

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L20-L25

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L27-L29

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L31-L32

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L34-L35

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L37-L64

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L66-L66

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L68-L131

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L134-L150

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L153-L174

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L176-L179

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L181-L181

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L182-L188

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L190-L190

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/fifo_v3.sv#L192-L192

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/include/cvxif_wrapper_pkg.sv#L9-L9

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/include/cvxif_wrapper_pkg.sv#L11-L11

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L25-L25

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L28-L35

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L37-L42

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L48-L48

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L56-L56

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L82-L82

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L89-L90

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L94-L95

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/lzc.sv#L109-L109

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L48-L84

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L86-L109

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L111-L111

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L113-L114

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L117-L118

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L120-L120

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L127-L127

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L132-L132

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L134-L135

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L138-L138

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L141-L144

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L146-L147

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L153-L153

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L155-L158

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L193-L193

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L196-L196

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L198-L198

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L201-L201

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L207-L209

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L212-L212

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L217-L218

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L220-L222

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L226-L227

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L229-L231

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L234-L235

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L238-L238

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L244-L244

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L247-L247

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L249-L249

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L254-L254

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L259-L259

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L263-L264

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L267-L267

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L269-L269

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L273-L273

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L277-L277

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L281-L281

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L283-L283

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[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L288-L288

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L293-L294

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L296-L296

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L299-L299

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L305-L306

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/rr_arb_tree.sv#L313-L313

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/wrapper_decoder.sv#L12-L12

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/wrapper_decoder.sv#L67-L67

---

[verible-verilog-format] _{reported by reviewdog 🐶}

https://github.com/openhwgroup/cva6/blob/9cc305bf650beb8e41da6de00df724a1f4ba7018/core/rb_cva6_copro_wrapper/rtl_v/wrapper_decoder.sv#L69-L69

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	instr: // custom1 opcode for CRC8, func2 = 01
	instr: // custom1 opcode for CRC8, func2 = 01

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	instr: // custom1 opcode for CRC16, func2 = 10, func3 = 001 or 011
	32'b 00000_10_00000_00000_0_01_00000_0101011,
	instr: // custom1 opcode for CRC16, func2 = 10, func3 = 001 or 011
	32'b00000_10_00000_00000_0_01_00000_0101011,

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	instr: // custom1 opcode for CRC32, func2 = 11, func3 = 011
	32'b 00000_11_00000_00000_0_11_00000_0101011,
	instr: // custom1 opcode for CRC32, func2 = 11, func3 = 011
	32'b00000_11_00000_00000_0_11_00000_0101011,

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	module instr_decoder import cvxif_pkg::*; #(
	parameter int NbInstr = 1,
	parameter cvxif_instr_pkg::copro_issue_resp_t CoproInstr[NbInstr] = {0}
	)
	(
	input logic clk_i,
	input x_issue_req_t x_issue_req_i,
	output x_issue_resp_t x_issue_resp_o
	module instr_decoder
	import cvxif_pkg::*;
	#(
	parameter int NbInstr = 1,
	parameter cvxif_instr_pkg::copro_issue_resp_t CoproInstr[NbInstr] = {0}
	) (
	input logic clk_i,
	input x_issue_req_t x_issue_req_i,
	output x_issue_resp_t x_issue_resp_o

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	assign sel[i] =
	((CoproInstr[i].mask & x_issue_req_i.instr) == CoproInstr[i].instr);
	assign sel[i] = ((CoproInstr[i].mask & x_issue_req_i.instr) == CoproInstr[i].instr);

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	endpackage
	endpackage

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam CVA6ConfigBExtEn = 1; // To be inserted in spec
	localparam CVA6ConfigBExtEn = 1; // To be inserted in spec

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam CVA6ConfigDataUserEn = 0; // Not compatible with current implemention, DISABLED
	localparam CVA6ConfigDataUserEn = 0; // Not compatible with current implemention, DISABLED

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam CVA6ConfigDcacheByteSize = 32768; // To be inserted in spec
	localparam CVA6ConfigDcacheByteSize = 32768; // To be inserted in spec

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	localparam CVA6ConfigDcacheLineWidth = 128; // To be inserted in spec
	localparam CVA6ConfigDcacheLineWidth = 128; // To be inserted in spec

[JeanRochCoulon]

@ntribie-bosch To become contributor, you need to sign the Eclipse agreement. The Verible command to fix errors is given in CONTRIBUTING.md file.

[ntribie-bosch]

Hi JR , thanks for your comment . I signed the agreement but our repo (github.com/boschglobal/cva6) is sending different credentials than the ones I used to sign it . I need to sort this out.

[cainria]

Hi Nicolas,

Authorship information is not modified by the repository (it is part of the commit hash so this is immutable).
If you created your commits via the git commit command line, it might be a git config issue (git config user.email can help).
If you created commits via GitHub, your account settings are here: https://github.com/settings/emails

In both cases, the branch needs to be rebased to update authorship information. https://stackoverflow.com/questions/16217801/git-rebase-change-author#16218264

[ntribie-bosch]

Hi Come, thanks for your comment. In fact this is a chicken <=> egg issue : I have to commit with this identity in our forked repo BoschGlobal , otherwise commits are rejected. But I didn't sign the eclipse agreement with this ID.. need to think how to handle this.

[cainria]

Is it possible to sign the ECA again with this email address?

[github-actions]

👋 Hi there!

This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊

[cainria]

Hi @ntribie-bosch

Have you found a way to fix the Eclipse ECA issues?