Raise illegal instruction exception for HFENCE.VVMA/HFENCE.GVMA when in V=1 mode and rd!=0

[antonangeloff]

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Summary

As indicated by #3462 - the HFENCE.VVMA/HFENCE.GVMA instructions having non-zero rd bits currently trigger virtual instruction exception (mcause 22) instead of illegal instruction (mcause 2) in V=1 mode.

The changes in this PR make HFENCE.* raise mcause=2 exception in the above case, which is consistent with Spike. The assumption being that non-zero rd bits would cause the instruction to be ill-formed (not HS-qualified).

Well formed HFENCE.* instructions are unaffected and still raise a virtual instruction exception under V=1.

The test can be run via:

export DV_SIMULATORS=veri-testharness,spike
cd verif/sim
source setup-env.sh
python3 cva6.py --testlist=../tests/testlist_issues.yaml --test hfence-rd-non-zero-rv64 --iss_yaml cva6.yaml --target cv64a6_imafdch_sv39 --iss=$DV_SIMULATORS

Related issues

Fixes #3462