plat-qcom: nord: add PIL bring-up for HPASS, SOCCP and Turing DSPs by taniyadas20 · Pull Request #41 · qualcomm-linux/optee_os

Taniya Das (taniyadas20) · 2026-08-12T10:54:47Z

Add the clock and PAS bring-up support required to load the additional DSP images on the Nord platform:

clock-qcom: add a Lucid-OLE PLL enable helper. Lucid-OLE reuses the Lucid-EVO register layout but packs PLL_L_VAL as an 8-bit L value plus separate 8-bit process-cal and ring-osc-cal fields, and requires the PLL_TEST_CTL* trim registers to be programmed, so it gets its own config struct and enable path.
clk_qcom: add QCOM_CLKS_{SOCCP,HPASS0,HPASS1,HPASS2,TURING2,TURING3} clock groups and route them through the PAS enable path.
pas_data: add PAS IDs for TURING2/3, HPASS0-2 and SOCCP.
nord: add the per-platform clock-qcom-pas.c and clock_group_qcom.h describing the PLL and clock-group configuration for these subsystems.
arch/target config: add the register base/size definitions needed by the new bring-up code.

Organizes PAS clock support under platform/$(PLATFORM_FLAVOR)/ so future platforms can provide their own PAS clock implementation. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Move all Kodiak-specific logic and the PTA command handlers into platform/kodiak/, and model each subsystem with a descriptor/ops abstraction: every platform exposes a table via qcom_pas_platform_subsys() that the generic pas_core.c drives. Pure structural refactor. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Add qcom_clock_lucidevo_pll_enable(), a self-contained helper that configures, locks and enables the main output of a Lucid-EVO PLL given its register block base and a struct qcom_lucidevo_pll_config. No caller yet; this provides the building block for per-processor PLL bring-up. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Bring up the Compute DSP (CDSP0/1) via the PAS peripheral authentication path on the Lemans platform. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Each PAS subsystem maps its controller window at runtime via core_mmu_add_mapping(); these late mappings come from CFG_RESERVED_VASPACE_SIZE and are never released. The six DSP windows total ~146.5 MB but the previous 60 MB default fits only one, so reserve 256 MB to cover them with headroom. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Add LPASS / ADSP (QDSP6 v68/v69) PAS bring-up for the Lemans platform (IQ-9075-EVK), following the existing Lemans CDSP0/1 PAS + clock-driver pattern and the Kodiak LPASS PTA layout. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

After boot the static memory map is frozen at count + 5 entries, so core_mmu_add_mapping() failed once those spare slots were exhausted. Grow the map through the same realloc hook as every other add path, re-resolving RES_VASPACE afterwards. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Add the IRIS video-codec PAS driver for lemans, mirroring the kodiak venus driver (which already targets IRIS hardware). The lemans IRIS register layout is identical: WRAPPER_TZ at IRIS+0xc0000 with the same XTSS_SW_RESET / FW / CPA / NONPIX offsets. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Add PAS bring-up for the two general-purpose Hexagon DSPs on Lemans (SA8775P): GP-DSP0 (TURINGGDSP, image id 39) and GP-DSP1 (TURINGGDSP1, image id 40). This follows the same architecture as the existing CDSP0/1, LPASS and IRIS subsystems. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

The subsystem manages the Iris video core, so name the file and its symbols accordingly to match the hardware it drives. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Move the PAS_ID_* definitions out of the per-platform target_config.h files into the PTA's pas_data.h so they live in one place. These IDs are really part of the PTA contract with the client rather than a platform definition; centralizing them in the PTA is a first step towards that abstraction. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Add io_read32_off()/io_write32_off() for reading/writing a 32-bit MMIO register at a base address plus byte offset, and io_read32_off_field()/io_write32_off_field() for getting/setting a masked, shifted field within such a register. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>

Add a driver for the Qualcomm Hardware Key Manager (HWKM), a hardware IP block present on Qualcomm SoCs that manages cryptographic key slots in a tamper-resistant key table. Keys stored in HWKM slots are never exposed in plaintext to software above the security level they were provisioned at; the hardware enforces per-slot access-control and usage policies. The driver exposes the following functionality to OP-TEE: - Hardware Unique Key (HUK): implements tee_otp_get_hw_unique_key() by performing a three-level key derivation using the SYSTEM_KDF command. A stable SKDK L3 mixing key is first derived from TZ_SKDK_L2 into the dedicated mixing key slot; the UKDK L3 KDK and the final L4 HUK are then derived with the mixing key folded in via BSVE.MKS_EN. Two Kconfig options control this behaviour: CFG_HWKM_HUK_MIX_SKDK (default y) enables the SKDK mixing step, and CFG_HWKM_HUK_FUSE_REGION_DIGEST (default 0x0) selects fuse regions whose SHA256 digest is bound into the KDF input. - Full command set: NIST_KEYGEN, SYSTEM_KDF, KEY_WRAP_EXPORT, KEY_UNWRAP_IMPORT, KEY_SLOT_CLEAR, KEY_SLOT_RDWR, and SET_TPKEY are all implemented and exposed through a transaction queue API. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add a MAINTAINERS entry for the new Qualcomm Hardware Key Manager (HWKM) driver. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add the HWKM master register region base and size to the shared Hoya architecture config so all Hoya-family targets can reference them, and enable CFG_QCOM_HWKM by default for the lemans target. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Standardize RNG driver naming and configuration across QCOM platforms.Rename prng.c to qcom-csrng.c and consolidate driver inclusion in the parent qcom/sub.mk with the unified CFG_QCOM_CSRNG flag.This change simplifies the driver structure and aligns with platform-agnostic naming conventions. The QCOM RNG IPs are confirmed by the hardware team to be cryptographically secure (CSRNG), so the driver is named qcom-csrng.c and enabled via CFG_QCOM_CSRNG to explicitly reflect that the source is safe for key generation. Update hoya chipset configurations to use the new CFG_QCOM_CSRNG flag and configure QCOM_RNG_REG_BASE for PRNG variant support, ensuring backward compatibility while establishing consistent naming standards across the codebase. Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Configure QCOM_RNG_REG_BASE and enable the consolidated RNG driver for the Bobcat family (ipq52xx). Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. When HWRNG_PTA is enabled: - Configure HWRNG quality to 1024 bits entropy - Set HWRNG rate to 0 (unlimited) Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

QCOM platforms manage secure watchdog via driver_init() without framework registration. This is sufficient as QCOM currently does not require HLOS control over the secure watchdog. The implementation maintains separation between secure and non-secure world watchdog management. The implementation maps the watchdog base (QCOM_WDT_TMR_BASE) into secure I/O memory, configures bark and bite timeouts using a 32 KHz clock, registers a bark interrupt handler, and services the watchdog by writing to the reset register. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

CFG_QCOM_SEC_WDOG is enabled in bobcat/arch.mk for all Bobcat targets, with platform-specific watchdog base addresses, interrupt IDs, and reset offsets defined in the respective target_config.h files (e.g., ipq96xx/ipq54xx and ipq52xx variants). Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

The Camera ICP (Imaging Control Processor, PAS ID 33) firmware must be loaded and authenticated by OP-TEE before CAMX can use the camera subsystem on SA8775P / Lemans EVK. Without this support the kernel camera driver fails to bring up the ICP and camera preview is unavailable. Add PAS reset ops for the ICP, register the subsystem in the PAS table. Tested: camera preview use case exercised on Lemans EVK; ICP firmware loads, authenticates and executes correctly with camera preview confirmed functional end-to-end. Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com>

TZDRAM and the DIAG log are currently protected by TF-A's static XPU policy, duplicating values OP-TEE already owns. Move ownership to OP-TEE for a single source of truth. Add an XPU4 driver: xpu_protect_region() takes a region and access policy, and resolves the XPU instance and a free resource group itself. It has no external callers, so it stays static. Both regions are protected from one service_init() call. DIAG log protection is skipped when CFG_QCOM_DIAG_LOG is disabled, so an unused buffer doesn't consume a resource group. Compiles only when CFG_QCOM_XPUV4 is enabled. Testing: XPU resource-group registers matched the expected TZDRAM/DIAG log ranges and permissions. Non-secure accesses raised XPU violations. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>

Enable OP-TEE-owned XPU protection for TZDRAM and the DIAG log on the Bobcat family (IPQ52xx, IPQ96xx), replacing TF-A's static policy for these regions. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>

Jorge A. Ramirez-Ortiz (ldts) · 2026-08-12T11:53:08Z

Please modify the commit messages removing the how the change is done as to why the change is needed.
also please describe how this code was tested so that I can reproduce on my end.

Copilot

Pull request overview

Adds Nord clock and reset sequencing for HPASS, SOCCP, and Turing DSP bring-up.

Changes:

Adds Lucid-OLE PLL configuration and enable support.
Adds PAS IDs, clock groups, and subsystem bring-up sequences.
Defines Nord MMIO regions and clock/reset registers.

Reviewed changes

Copilot reviewed 7 out of 7 changed files in this pull request and generated 5 comments.

Show a summary per file

File	Description
`core/pta/qcom/pas/platform/pas_data.h`	Adds subsystem PAS IDs.
`core/include/drivers/clk_qcom.h`	Adds clock groups and Lucid-OLE API.
`core/drivers/clk/qcom/platform/nord/clock-qcom-pas.c`	Implements Nord clock, reset, and processor sequencing.
`core/drivers/clk/qcom/platform/nord/clock_group_qcom.h`	Defines Nord clock/reset registers.
`core/drivers/clk/qcom/clock-qcom.c`	Implements Lucid-OLE PLL enablement and routing.
`core/arch/arm/plat-qcom/wildcat/nord/target_config.h`	Adds Nord peripheral MMIO regions.
`core/arch/arm/plat-qcom/wildcat/arch_config.h`	Adds Wildcat architecture register regions.

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+	/* 6. Wait for the FSM to auto-break. */
+	while (!(io_read32(pub + CDSP_QDSP6SS_BOOT_STATUS) &
+		 QDSP6SS_BOOT_STATUS_AUTO_BREAK_BIT))
+		udelay(5);


+{
+	uint64_t timeout = 0;
+
+	io_clrbits32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QREQN, qreqn_bit);
+	timeout = timeout_init_us(500);
+	while (io_read32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QACCEPTN) &
+	       qaccept_bit) {
+		if (timeout_elapsed(timeout))
+			goto retry;
+		udelay(5);
+	}
+	return TEE_SUCCESS;
+
+retry:
+	if (!(io_read32(tcsr + TCSR_HPASS_AG_NOC_QCHANNEL_QACCEPTN) &
+	      qdeny_bit))
+		return TEE_SUCCESS;


+
+#define TCSR_HPASS_AG_NOC_QDENY_BIT		BIT(1)
+#define TCSR_HPASS_ENPU_NOC_QDENY_BIT		BIT(5)
+#define TCSR_HPASS_AUDIO_NOC_QDENY_BIT		TCSR_HPASS_AG_NOC_QDENY_BIT


+	while (!timeout_elapsed(timeout)) {
+		if (io_read32(v + HPASS_QDSP6SS_BOOT_STATUS) &
+		    QDSP6SS_BOOT_STATUS_AUTO_BREAK_BIT)
+			break;
+		udelay(5);
+	}


+	return TEE_SUCCESS;
+}
+
+TEE_Result qcom_clock_enable_pas(enum qcom_clk_group group)


A stale carveout could be reused across peripheral loads: shutdown did not clear the cached MEM_SETUP coordinates, so a subsystem that was stopped and reloaded without a fresh MEM_SETUP call would pass the resulting VERIFY_IMAGE cross-check against physical memory it no longer owns. qcom_pas_capabilities() also passed the wrong parameter to pas_platform_capabilities(), reading the output flags field instead of the caller-supplied pas_id. Fix both ahead of the authentication work that builds on this code, along with unrelated include and logging cleanup, so the feature commits that follow stay focused on the feature. pas_lookup() is exported for the same reason: later commits need it directly. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

PIL firmware images carry a Qualcomm MBN hash segment holding the per-segment digest table, signature and certificate material the PAS TA needs to authenticate an image before releasing the peripheral from reset. Introduce a parser for this segment so the authentication phases that follow can consume a single, structured view of it rather than each phase re-parsing the raw metadata buffer independently and risking disagreement about region boundaries. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

A compromised REE could substitute firmware in the peripheral's carveout between the point image metadata is accepted and the point the peripheral is released from reset. Add a verification step that re-hashes each loaded segment against the image's own digest table and fails closed on any mismatch, so the peripheral only runs code whose bytes match what was authenticated. Provide it as a standalone capability so hash verification can be enabled and reviewed independently of signature authentication. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Segment-hash verification lives in the PTA but nothing invokes it today, so a peripheral can be released from reset without any TEE-side check that the firmware in its carveout is what was authenticated. Bridge that gap: the TA captures a TEE-private copy of the REE-supplied metadata at image-init time and drives the verifier with it at reset time, so the REE cannot mutate the metadata the check runs against between the two events. Per-peripheral state is keyed by ID so concurrent bring-ups on the same session do not clobber each other. Signature authentication is left as a placeholder so segment-hash verification can land and be reviewed without waiting on it. Release the captured metadata when a peripheral is shut down, so it does not remain allocated for the life of the session after the peripheral it authenticated is torn down. The per-ID slot itself is retained because slots are provisioned one per peripheral; reclaiming it would break the capacity model when the same peripheral is reloaded later. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Enable CFG_QCOM_PAS_AUTH on Lemans so PIL images are authenticated before the peripheral leaves reset. Segment-hash verification takes effect immediately; signature authentication is a runtime step that only engages once secure-boot fuses are blown, and is filled in later in this series. Signed-off-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Assisted-by: Claude:sonnet-5 Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Basant Kumar (basantku) · 2026-08-13T08:09:07Z

 #define TARGET_CONFIG_H

-#define GENI_UART_REG_BASE		UL(0x884000)
+#define GCC_BASE			UL(0x110000)


Please explicit add some tag like WIP, if change is not tested. It will help to avoid review confusion.

Sure, will add WIP

Basant Kumar (basantku) · 2026-08-13T08:11:01Z

+#define SE_GCC_CBCR_CLK_OFF_BIT			BIT(31)
+#define SE_GCC_CBCR_HW_CTL_ENABLE_BIT		BIT(1)
+
+#define CDSP_NSP_SS_CC_OFFSET			0x00000000


for one group of #define can follow same indent for macro value?

Selvam (zelvam95) · 2026-08-13T08:13:00Z

If this change is not tested, can you please move the PR to draft Taniya Das (@taniyadas20). We can mark it as ready to review once all the dependent parts are avail/change is ready to review.

…files Nord was the only Wildcat chip in the tree, so its GIC base addresses and DARE-TZ TZDRAM region settings were placed in the shared Wildcat architecture layer. Adding a second Wildcat chip with different addresses makes the architecture layer the wrong home for them. Move GICD_BASE and GICR_BASE from arch_config.h to nord/target_config.h, and move the DARE-TZ TZDRAM region configuration from qcom-arch.mk to nord/target.mk, so the shared Wildcat layer stays chip-agnostic. Add SPDX licence identifier to qcom-arch.mk while there. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Cacao is a Qualcomm XR chipset in the Wildcat architecture family, featuring an octa-core Oryon CPU, a GICv4 interrupt controller, and DARE-TZ in-line memory encryption managed by the TME root-of-trust. OP-TEE runs in a DARE-TZ protected DRAM region and does not need a separate DARE driver. Testing: Tested on Rumi. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

This reverts commit d06baae.

This reverts commit d74ee55.

This reverts commit 1c89e2f.

This reverts commit c297c66.

This reverts commit d3a0500.

Shikra is a Qualcomm IoT chipset in the Bruin architecture family, featuring a quad-core Cortex-A55 CPU and a GICv3 interrupt controller. Tested optee boot-up on Shikra board. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Harshal Dev <harshal.dev@oss.qualcomm.com> Tested-by: Harshal Dev <harshal.dev@oss.qualcomm.com>

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Add the clock and PAS bring-up support required to load the additional DSP images on the Nord platform: - clock-qcom: add a Lucid-OLE PLL enable helper. Lucid-OLE reuses the Lucid-EVO register layout but packs PLL_L_VAL as an 8-bit L value plus separate 8-bit process-cal and ring-osc-cal fields, and requires the PLL_TEST_CTL* trim registers to be programmed, so it gets its own config struct and enable path. - clk_qcom: add QCOM_CLKS_{SOCCP,HPASS0,HPASS1,HPASS2,TURING2,TURING3} clock groups and route them through the PAS enable path. - pas_data: add PAS IDs for TURING2/3, HPASS0-2 and SOCCP. - nord: add the per-platform clock-qcom-pas.c and clock_group_qcom.h describing the PLL and clock-group configuration for these subsystems. - arch/target config: add the register base/size definitions needed by the new bring-up code. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>

spalepuqual · 2026-08-28T07:02:45Z

We need to checkin soccp.c as well to enable SoCCP PIL

Signed-off-by: pawarai123 <pawarai@qti.qualcomm.com>

Jorge A. Ramirez-Ortiz (ldts) and others added 22 commits July 21, 2026 18:34

qcom: pas: lemans: enable CDSP0/1 PAS support

b6ccd16

Bring up the Compute DSP (CDSP0/1) via the PAS peripheral authentication path on the Lemans platform. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>

Taniya Das (taniyadas20) force-pushed the nord-pil-support branch from dd0a6f2 to 895c213 Compare August 12, 2026 11:03

Jorge A. Ramirez-Ortiz (ldts) requested a balanced review from Copilot August 12, 2026 11:53

Copilot started reviewing on behalf of Jorge A. Ramirez-Ortiz (ldts) August 12, 2026 11:56 View session

Copilot AI reviewed Aug 12, 2026

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Selvam (zelvam95) added 3 commits August 12, 2026 21:02

Selvam (zelvam95) added 2 commits August 12, 2026 21:02

Basant Kumar (basantku) reviewed Aug 13, 2026

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Taniya Das (taniyadas20) marked this pull request as draft August 14, 2026 05:10

pawarai123 and others added 10 commits August 19, 2026 18:17

ci: qcom: add cacao platform build

d4f0de6

Add PLATFORM=qcom-cacao build to the CI. Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com>

Revert "plat-qcom: hoya: lemans: enable PAS firmware authentication"

0d5e016

This reverts commit d06baae.

Revert "ta: qcom_pas: verify loaded firmware image integrity"

55e00f6

This reverts commit d74ee55.

Revert "pta: qcom: pas: add firmware segment hash verification"

eef6e25

This reverts commit 1c89e2f.

Revert "ta: qcom_pas: add Multiboot Binary (MBN) hash-segment parser"

d71b58a

This reverts commit c297c66.

Revert "pta: qcom: pas: preparatory fixes and cleanup"

1fd4412

This reverts commit d3a0500.

ci: qcom: add shikra platform build

ca169e2

Add PLATFORM=qcom-shikra build to the CI. Signed-off-by: Pawan Rai <pawarai@qti.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>

Taniya Das (taniyadas20) force-pushed the nord-pil-support branch from 895c213 to df4797d Compare August 27, 2026 10:11

Taniya Das (taniyadas20) force-pushed the nord-pil-support branch from df4797d to b288980 Compare August 27, 2026 10:32

spalepuqual reviewed Aug 28, 2026

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Comment thread core/drivers/clk/qcom/platform/nord/clock-qcom-pas.c

spalepuqual Aug 28, 2026

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We need to checkin soccp.c as well to enable SoCCP PIL

Merge branch 'qcom-next' into nord-pil-support

1f26ca0

Signed-off-by: pawarai123 <pawarai@qti.qualcomm.com>

Sumit Garg (b49020) force-pushed the qcom-next branch 2 times, most recently from 1a117cb to dab3efd Compare September 7, 2026 07:43

Deepak kumar (deepaknasir) mentioned this pull request Sep 10, 2026

plat-qcom: nord: enable HPASS0-2/NSPSS0-3 PAS support #67

Open

praspank-qcom mentioned this pull request Sep 10, 2026

pta: qcom: pas: nord: add aperture resource tables for HPASS and NSP praspank-qcom/optee_os#1

Open

Deepak kumar (deepaknasir) mentioned this pull request Sep 17, 2026

Topic/my feature branch #72

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plat-qcom: nord: add PIL bring-up for HPASS, SOCCP and Turing DSPs - #41

plat-qcom: nord: add PIL bring-up for HPASS, SOCCP and Turing DSPs#41
Taniya Das (taniyadas20) wants to merge 39 commits into
qualcomm-linux:qcom-nextfrom
taniyadas20:nord-pil-support

Taniya Das (taniyadas20) commented Aug 12, 2026

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Jorge A. Ramirez-Ortiz (ldts) commented Aug 12, 2026

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Basant Kumar (basantku) Aug 13, 2026

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Taniya Das (taniyadas20) Aug 14, 2026

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Selvam (zelvam95) commented Aug 13, 2026

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Taniya Das (taniyadas20) commented Aug 12, 2026

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Jorge A. Ramirez-Ortiz (ldts) commented Aug 12, 2026

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Basant Kumar (basantku) Aug 13, 2026

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Taniya Das (taniyadas20) Aug 14, 2026

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Basant Kumar (basantku) Aug 13, 2026

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Selvam (zelvam95) commented Aug 13, 2026

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spalepuqual Aug 28, 2026

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