drivers: qcom: add RPM client for Shikra - #59
Draft
IDineshChoudhary wants to merge 23 commits into
Draft
IDineshChoudhary wants to merge 23 commits into
IDineshChoudhary wants to merge 23 commits into
Conversation
Organizes PAS clock support under platform/$(PLATFORM_FLAVOR)/ so future platforms can provide their own PAS clock implementation. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Move all Kodiak-specific logic and the PTA command handlers into platform/kodiak/, and model each subsystem with a descriptor/ops abstraction: every platform exposes a table via qcom_pas_platform_subsys() that the generic pas_core.c drives. Pure structural refactor. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add qcom_clock_lucidevo_pll_enable(), a self-contained helper that configures, locks and enables the main output of a Lucid-EVO PLL given its register block base and a struct qcom_lucidevo_pll_config. No caller yet; this provides the building block for per-processor PLL bring-up. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Bring up the Compute DSP (CDSP0/1) via the PAS peripheral authentication path on the Lemans platform. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Each PAS subsystem maps its controller window at runtime via core_mmu_add_mapping(); these late mappings come from CFG_RESERVED_VASPACE_SIZE and are never released. The six DSP windows total ~146.5 MB but the previous 60 MB default fits only one, so reserve 256 MB to cover them with headroom. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add LPASS / ADSP (QDSP6 v68/v69) PAS bring-up for the Lemans platform (IQ-9075-EVK), following the existing Lemans CDSP0/1 PAS + clock-driver pattern and the Kodiak LPASS PTA layout. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
After boot the static memory map is frozen at count + 5 entries, so core_mmu_add_mapping() failed once those spare slots were exhausted. Grow the map through the same realloc hook as every other add path, re-resolving RES_VASPACE afterwards. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add the IRIS video-codec PAS driver for lemans, mirroring the kodiak venus driver (which already targets IRIS hardware). The lemans IRIS register layout is identical: WRAPPER_TZ at IRIS+0xc0000 with the same XTSS_SW_RESET / FW / CPA / NONPIX offsets. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add PAS bring-up for the two general-purpose Hexagon DSPs on Lemans (SA8775P): GP-DSP0 (TURINGGDSP, image id 39) and GP-DSP1 (TURINGGDSP1, image id 40). This follows the same architecture as the existing CDSP0/1, LPASS and IRIS subsystems. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
The subsystem manages the Iris video core, so name the file and its symbols accordingly to match the hardware it drives. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Move the PAS_ID_* definitions out of the per-platform target_config.h files into the PTA's pas_data.h so they live in one place. These IDs are really part of the PTA contract with the client rather than a platform definition; centralizing them in the PTA is a first step towards that abstraction. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Add io_read32_off()/io_write32_off() for reading/writing a 32-bit MMIO register at a base address plus byte offset, and io_read32_off_field()/io_write32_off_field() for getting/setting a masked, shifted field within such a register. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Add a driver for the Qualcomm Hardware Key Manager (HWKM), a hardware
IP block present on Qualcomm SoCs that manages cryptographic key slots
in a tamper-resistant key table. Keys stored in HWKM slots are never
exposed in plaintext to software above the security level they were
provisioned at; the hardware enforces per-slot access-control and
usage policies.
The driver exposes the following functionality to OP-TEE:
- Hardware Unique Key (HUK): implements tee_otp_get_hw_unique_key()
by performing a three-level key derivation using the SYSTEM_KDF
command. A stable SKDK L3 mixing key is first derived from
TZ_SKDK_L2 into the dedicated mixing key slot; the UKDK L3 KDK
and the final L4 HUK are then derived with the mixing key folded
in via BSVE.MKS_EN. Two Kconfig options control this behaviour:
CFG_HWKM_HUK_MIX_SKDK (default y) enables the SKDK mixing step,
and CFG_HWKM_HUK_FUSE_REGION_DIGEST (default 0x0) selects fuse
regions whose SHA256 digest is bound into the KDF input.
- Full command set: NIST_KEYGEN, SYSTEM_KDF, KEY_WRAP_EXPORT,
KEY_UNWRAP_IMPORT, KEY_SLOT_CLEAR, KEY_SLOT_RDWR, and SET_TPKEY
are all implemented and exposed through a transaction queue API.
Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com>
Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Add a MAINTAINERS entry for the new Qualcomm Hardware Key Manager (HWKM) driver. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Add the HWKM master register region base and size to the shared Hoya architecture config so all Hoya-family targets can reference them, and enable CFG_QCOM_HWKM by default for the lemans target. Signed-off-by: Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> Acked-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com>
Standardize RNG driver naming and configuration across QCOM platforms.Rename prng.c to qcom-csrng.c and consolidate driver inclusion in the parent qcom/sub.mk with the unified CFG_QCOM_CSRNG flag.This change simplifies the driver structure and aligns with platform-agnostic naming conventions. The QCOM RNG IPs are confirmed by the hardware team to be cryptographically secure (CSRNG), so the driver is named qcom-csrng.c and enabled via CFG_QCOM_CSRNG to explicitly reflect that the source is safe for key generation. Update hoya chipset configurations to use the new CFG_QCOM_CSRNG flag and configure QCOM_RNG_REG_BASE for PRNG variant support, ensuring backward compatibility while establishing consistent naming standards across the codebase. Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Configure QCOM_RNG_REG_BASE and enable the consolidated RNG driver for the Bobcat family (ipq52xx). Force enable CFG_QCOM_CSRNG to use the hardware QRNG driver, and disable CFG_WITH_SOFTWARE_PRNG whenever CFG_QCOM_CSRNG is enabled to prevent fallback to the software PRNG. When HWRNG_PTA is enabled: - Configure HWRNG quality to 1024 bits entropy - Set HWRNG rate to 0 (unlimited) Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
QCOM platforms manage secure watchdog via driver_init() without framework registration. This is sufficient as QCOM currently does not require HLOS control over the secure watchdog. The implementation maintains separation between secure and non-secure world watchdog management. The implementation maps the watchdog base (QCOM_WDT_TMR_BASE) into secure I/O memory, configures bark and bite timeouts using a 32 KHz clock, registers a bark interrupt handler, and services the watchdog by writing to the reset register. Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
CFG_QCOM_SEC_WDOG is enabled in bobcat/arch.mk for all Bobcat targets, with platform-specific watchdog base addresses, interrupt IDs, and reset offsets defined in the respective target_config.h files (e.g., ipq96xx/ipq54xx and ipq52xx variants). Signed-off-by: Harikrishna <hart@qti.qualcomm.com> Reviewed-by: Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
The Camera ICP (Imaging Control Processor, PAS ID 33) firmware must be loaded and authenticated by OP-TEE before CAMX can use the camera subsystem on SA8775P / Lemans EVK. Without this support the kernel camera driver fails to bring up the ICP and camera preview is unavailable. Add PAS reset ops for the ICP, register the subsystem in the PAS table. Tested: camera preview use case exercised on Lemans EVK; ICP firmware loads, authenticates and executes correctly with camera preview confirmed functional end-to-end. Signed-off-by: Ignatius Michael Jihan <mignatiu@qti.qualcomm.com>
TZDRAM and the DIAG log are currently protected by TF-A's static XPU policy, duplicating values OP-TEE already owns. Move ownership to OP-TEE for a single source of truth. Add an XPU4 driver: xpu_protect_region() takes a region and access policy, and resolves the XPU instance and a free resource group itself. It has no external callers, so it stays static. Both regions are protected from one service_init() call. DIAG log protection is skipped when CFG_QCOM_DIAG_LOG is disabled, so an unused buffer doesn't consume a resource group. Compiles only when CFG_QCOM_XPUV4 is enabled. Testing: XPU resource-group registers matched the expected TZDRAM/DIAG log ranges and permissions. Non-secure accesses raised XPU violations. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>
Enable OP-TEE-owned XPU protection for TZDRAM and the DIAG log on the Bobcat family (IPQ52xx, IPQ96xx), replacing TF-A's static policy for these regions. Tested-on: Hermosa (IPQ52xx) Tested-on: Juhu (IPQ96xx) Signed-off-by: Harikrishna <hart@qti.qualcomm.com>
Sumit Garg (b49020)
force-pushed
the
qcom-next
branch
2 times, most recently
from
September 7, 2026 07:43
1a117cb to
dab3efd
Compare
Member
|
Please rebase this PR to tip of qcom-next. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
6 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Summary
Test