drivers: qcom: add RPM client for Shikra

MAINTAINERS

@@ -146,6 +146,11 @@ S:	Maintained
 F:	core/drivers/qcom/cmd_db/
 F:	core/include/drivers/qcom/cmd_db/
 
+Core Drivers QCOM HWKM
+R:	Amirreza Zarrabi <amirreza.zarrabi@oss.qualcomm.com> [@qc-azarrabi]
+S:	Maintained
+F:	core/drivers/crypto/qcom/
+
 Core Drivers QCOM QFPROM
 R:	Selvam Sathappan Periakaruppan <speriaka@qti.qualcomm.com> [@zelvam95]
 R:	Kishore Batta <kishore.batta@oss.qualcomm.com> [@kishorebatta-ossqcom]

core/arch/arm/plat-qcom/bobcat/ipq52xx/target.mk

@@ -6,3 +6,10 @@ CFG_QCOM_DIAG_LOG ?= $(CFG_TEE_CORE_DEBUG)
 CFG_TZDRAM_START ?= 0x87D80000
 CFG_TZDRAM_SIZE ?= 0x280000
 CFG_TEE_RAM_VA_SIZE ?= 0x280000
+
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
+
+CFG_HWRNG_PTA ?= y
+CFG_HWRNG_QUALITY ?= 1024
+CFG_HWRNG_RATE ?= 0

core/arch/arm/plat-qcom/bobcat/ipq52xx/target_config.h

@@ -20,4 +20,9 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x18000)
 
+#define QCOM_RNG_REG_BASE		UL(0x4C5000)
+
+#define QCOM_WDT_TMR_BASE		UL(0x0B117000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x23)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/ipq96xx/target_config.h

@@ -19,4 +19,7 @@
 #define IMEM_BASE			UL(0x8600000)
 #define IMEM_SIZE			UL(0x20000)
 
+#define QCOM_WDT_TMR_BASE		UL(0x0F411000)
+#define QCOM_WDT_BARK_INT_ID		UL(0x36)
+
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bobcat/qcom-arch.mk

@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-2-Clause
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+
+CFG_QCOM_SEC_WDOG ?= y
+
+# XPU protection for TZDRAM and the OP-TEE DIAG log buffer
+CFG_QCOM_XPUV4 ?= y

core/arch/arm/plat-qcom/bruin/arch_config.h

@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef ARCH_CONFIG_H
+#define ARCH_CONFIG_H
+
+#define GICD_BASE			UL(0x17000000)
+#define GICR_BASE			UL(0x17080000)
+
+#endif /* ARCH_CONFIG_H */

core/arch/arm/plat-qcom/bruin/core_pos_a64.S

@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ *
+ * Oryon MPIDR has the MT bit set but uses one thread per core with
+ * AFF0 = thread (always 0), AFF1 = core (0..5), AFF2 = cluster (0..2).
+ * The generic get_core_pos_mpidr left-shifts the MPIDR by one affinity
+ * level when MT is set; on this layout that promotes the CORE into the
+ * cluster slot and drops the real cluster. Read AFF1/AFF2 from the raw MPIDR
+ * instead and produce a contiguous CorePos = cluster * 6 + core.
+ */
+
+#include <asm.S>
+#include <arm.h>
+#include <arm64_macros.S>
+
+FUNC get_core_pos_mpidr , :
+	/* AFF1 = core (0..5) */
+	ubfx	x1, x0, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
+	/* AFF2 = cluster (0..2) */
+	ubfx	x2, x0, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
+	add	x2, x2, x2, lsl #1	/* x2 = cluster * 3 */
+	add	x0, x1, x2, lsl #1	/* CorePos = core + cluster * 6 */
+	ret
+END_FUNC get_core_pos_mpidr

core/arch/arm/plat-qcom/bruin/qcom-arch.mk

@@ -0,0 +1,11 @@
+# Shikra architecture configuration
+
+include core/arch/arm/cpu/cortex-armv8-0.mk
+
+$(call force,CFG_ARM_GICV4,y)
+
+CFG_TZDRAM_START ?= 0xBC280000
+CFG_TEE_RAM_VA_SIZE ?= 0x00200000
+CFG_TA_RAM_VA_SIZE ?= 0x07B80000
+CFG_TZDRAM_SIZE ?= (CFG_TEE_RAM_VA_SIZE + CFG_TA_RAM_VA_SIZE)
+CFG_NUM_THREADS ?= 8

core/arch/arm/plat-qcom/bruin/shikra/target.mk

@@ -0,0 +1,7 @@
+# Shikra OP-TEE platform.
+
+# Threads are expensive in OP-TEE, so they don't have to match core count.
+$(call force,CFG_TEE_CORE_NB_CORE,18)
+
+$(call force,CFG_QCOM_RPM_CLIENT,y)
+CFG_QCOM_RPM_TRANSPORT_STUB ?= y

core/arch/arm/plat-qcom/bruin/shikra/target_config.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: BSD-2-Clause */
+/*
+ * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef TARGET_CONFIG_H
+#define TARGET_CONFIG_H
+
+#define GENI_UART_REG_BASE		UL(0x884000)
+
+#define DRAM0_BASE			UL(0x80000000)
+#define DRAM0_SIZE			UL(0x380000000)
+#define DRAM1_BASE			ULL(0x800000000)
+#define DRAM1_SIZE			ULL(0x800000000)
+
+#endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/bruin/sub.mk

@@ -0,0 +1 @@
+srcs-y += core_pos_a64.S

core/arch/arm/plat-qcom/conf.mk

@@ -32,13 +32,16 @@ supported-ta-targets ?= ta_arm64
 HOYA_ARCH_CHIPSETS := kodiak lemans
 BOBCAT_ARCH_CHIPSETS := ipq96xx ipq52xx
 WILDCAT_ARCH_CHIPSETS := nord
+BRUIN_ARCH_CHIPSETS := shikra
 
 ifneq (,$(filter $(PLATFORM_FLAVOR),$(HOYA_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := hoya
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(BOBCAT_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := bobcat
 else ifneq (,$(filter $(PLATFORM_FLAVOR),$(WILDCAT_ARCH_CHIPSETS)))
 QCOM_ARCH_FAMILY := wildcat
+else ifneq (,$(filter $(PLATFORM_FLAVOR),$(BRUIN_ARCH_CHIPSETS)))
+QCOM_ARCH_FAMILY := bruin
 else
 $(error Unsupported PLATFORM_FLAVOR: $(PLATFORM_FLAVOR))
 endif

core/arch/arm/plat-qcom/hoya/arch_config.h

@@ -11,7 +11,7 @@
 #define GICR_BASE			UL(0x17a60000)
 
 #define RAMBLUR_PIMEM_REG_BASE		UL(0x610000)
-#define SEC_PRNG_REG_BASE		UL(0x010D1000)
+#define QCOM_RNG_REG_BASE		UL(0x010D1000)
 
 #define AOP_MSG_RAM_BASE		UL(0x0C300000)
 #define AOP_MSG_RAM_SIZE		UL(0x00100000)
@@ -25,6 +25,9 @@
 #define TCSR_MUTEX_BASE			UL(0x01F40000)
 #define TCSR_MUTEX_SIZE			UL(0x40000)
 
+#define HWKM_MASTER_BASE		UL(0x010c0000)
+#define HWKM_MASTER_SIZE		UL(0x00020000)
+
 #define IMEM_DIAG_OFFSET		UL(0x720)
 #define DIAG_SIZE			UL(0x3000)
 #define DIAG_BASE			(IMEM_BASE + IMEM_SIZE - DIAG_SIZE)

core/arch/arm/plat-qcom/hoya/lemans/target.mk

@@ -12,3 +12,14 @@ $(call force,CFG_QCOM_CMD_DB,y)
 $(call force,CFG_QCOM_RPMH_CLIENT,y)
 $(call force,CFG_QCOM_QFPROM,y)
 endif
+
+CFG_QCOM_PAS_PTA ?= y
+
+ifeq ($(CFG_QCOM_PAS_PTA),y)
+# PAS subsystems map their controller windows at runtime from the reserved VA
+# pool (never released). The six DSP windows total ~146.5 MB; the 60 MB default
+# fits only one, so reserve 256 MB with headroom.
+CFG_RESERVED_VASPACE_SIZE ?= (256 * 1024 * 1024)
+CFG_IN_TREE_EARLY_TAS += qcom_pas/cff7d191-7ca0-4784-af13-48223b9a4fbe
+endif
+CFG_QCOM_HWKM ?= y

core/arch/arm/plat-qcom/hoya/lemans/target_config.h

@@ -30,4 +30,68 @@
 #define IMEM_BASE			UL(0x14680000)
 #define IMEM_SIZE			UL(0x32000)
 
+#define TURING_0_BASE			UL(0x24000000)
+#define TURING_0_SIZE			UL(0x03000000)
+
+#define TURING_1_BASE			UL(0x28000000)
+#define TURING_1_SIZE			UL(0x03000000)
+
+/*
+ * GP-DSP0 / GP-DSP1 (TURINGGDSP / TURINGGDSP1) subsystems. The window covers
+ * every GP-DSP sub-block the PTA and clock driver touch (GDSP_CC 0x808000, PUB
+ * 0xc00000, PLL 0xc40000, CORE_CC 0xc48000).
+ */
+#define TURING_GDSP_0_BASE		UL(0x20000000)
+#define TURING_GDSP_0_SIZE		UL(0x01000000)
+
+#define TURING_GDSP_1_BASE		UL(0x21000000)
+#define TURING_GDSP_1_SIZE		UL(0x01000000)
+
+/*
+ * LPASS / ADSP (QDSP6 v68/v69) subsystem window, covering every sub-block the
+ * PTA and clock driver touch (PUB, PLL, CORE_CC, AON_CC, MCC, TOP_CC).
+ */
+#define LPASS_BASE			UL(0x02c00000)
+#define LPASS_SIZE			ULL(0x01080000)
+
+/*
+ * IRIS video-codec subsystem. The window covers the VCODEC_IRIS_WRAPPER_TOP
+ * (IRIS+0xb0000) and WRAPPER_TZ (IRIS+0xc0000) blocks the bring-up path
+ * touches.
+ */
+#define IRIS_BASE			UL(0x0aa00000)
+#define IRIS_SIZE			ULL(0x00200000)
+
+/* CDSP0 content-protection shared channel (secure DDR); no CDSP1 equivalent. */
+#define CDSP_SECCHANNEL_BASE		UL(0xdb1dc000)
+#define CDSP_SECCHANNEL_SIZE		UL(0x2000)
+
+/*
+ * Global register blocks for the Turing/NSP reset sequence, under AOSS_BASE
+ * (0x0b000000). TCSR_MUTEX_BASE/SIZE is already defined in arch_config.h.
+ */
+#define AOSS_CC_BASE			UL(0x0c2a8000)
+#define AOSS_CC_SIZE			UL(0x00050000)
+
+#define RPMH_PDC_GLOBAL_BASE		UL(0x0b5e0000)
+#define RPMH_PDC_GLOBAL_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_COMPUTE_BASE		UL(0x0b2c0000)
+#define RPMH_PDC_COMPUTE_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_NSP_BASE		UL(0x0b2f0000)
+#define RPMH_PDC_NSP_SIZE		UL(0x00002000)
+
+/*
+ * RPMH PDC blocks for the GP-DSP subsystem reset sequence. These live under
+ * AOSS_BASE (0x0b000000), at offsets 0x240000 / 0x2d0000.
+ */
+#define RPMH_PDC_GPDSP0_BASE		UL(0x0b240000)
+#define RPMH_PDC_GPDSP0_SIZE		UL(0x00002000)
+
+#define RPMH_PDC_GPDSP1_BASE		UL(0x0b2d0000)
+#define RPMH_PDC_GPDSP1_SIZE		UL(0x00002000)
+
+#define TITAN_SS_BASE			UL(0x0ac00000)
+#define TITAN_SS_SIZE			UL(0x00200000)
 #endif /* TARGET_CONFIG_H */

core/arch/arm/plat-qcom/hoya/qcom-arch.mk

@@ -6,7 +6,8 @@ $(call force,CFG_TEE_CORE_NB_CORE,8)
 $(call force,CFG_QCOM_RAMBLUR_PIMEM_V3,y)
 CFG_QCOM_RAMBLUR_TA_WINDOW_ID ?= 2
 
-$(call force,CFG_QCOM_PRNG,y)
+$(call force,CFG_QCOM_CSRNG,y)
+$(call force,CFG_WITH_SOFTWARE_PRNG,n)
 $(call force,CFG_ARM_GICV3,y)
 
 CFG_TZDRAM_START ?= 0x1c300000

core/drivers/clk/qcom/clock-qcom.c

@@ -15,6 +15,41 @@ register_phys_mem(MEM_AREA_IO_NSEC, GCC_BASE, GCC_SIZE);
 #define CBCR_HW_CTL_ENABLE_BIT		BIT(1)
 #define CBCR_BRANCH_OFF_BIT		BIT(31)
 
+/* Lucid-EVO PLL register offsets, relative to the PLL register block base. */
+#define PLL_MODE			0x0
+#define PLL_OPMODE			0x4
+#define PLL_L_VAL			0x10
+#define PLL_ALPHA_VAL			0x14
+#define PLL_USER_CTL			0x18
+#define PLL_USER_CTL_U			0x1c
+#define PLL_CONFIG_CTL			0x20
+#define PLL_CONFIG_CTL_U		0x24
+#define PLL_CONFIG_CTL_U1		0x28
+
+/* PLL_MODE fields */
+#define PLL_MODE_OUTCTRL		BIT(0)
+#define PLL_MODE_RESET_N		BIT(2)
+#define PLL_MODE_LOCK_DET		BIT(31)
+
+/* PLL_OPMODE values */
+#define PLL_OPMODE_RUN			0x1
+
+/* PLL_L_VAL fields */
+#define PLL_L_VAL_L_MASK		0x0000ffff
+#define PLL_L_VAL_CAL_L_SHIFT		16
+#define PLL_L_VAL_CAL_L_MASK		0xffff0000
+
+/* PLL_USER_CTL fields */
+#define PLL_USER_CTL_PLLOUT_MAIN_EN	BIT(0)
+#define PLL_USER_CTL_PRE_DIV_SHIFT	22
+#define PLL_USER_CTL_PRE_DIV_MASK	0x01c00000
+#define PLL_USER_CTL_POST_DIV_ODD_MASK	0x0003c000
+#define PLL_USER_CTL_POST_DIV_EVEN_MASK	0x00003c00
+#define PLL_USER_CTL_FRAC_FORMAT_SEL	BIT(28)
+
+/* PLL_USER_CTL_U fields */
+#define PLL_USER_CTL_U_FINE_LOCK_DET	BIT(0)
+
 static inline bool cbcr_branch_on(uint32_t val)
 {
 	return !(val & CBCR_BRANCH_OFF_BIT);
@@ -26,6 +61,14 @@ TEE_Result qcom_clock_enable_cbc(vaddr_t cbcr)
 
 	io_setbits32(cbcr, CBCR_BRANCH_ENABLE_BIT);
 
+	/*
+	 * In hardware clock-control mode (HW_CTL set) CLK_OFF is driven by HW,
+	 * not the software CLK_ENABLE write, so skip the poll to avoid
+	 * spinning.
+	 */
+	if (io_read32(cbcr) & CBCR_HW_CTL_ENABLE_BIT)
+		return TEE_SUCCESS;
+
 	REG_POLL_TIMEOUT(cbcr, 10 * 1000, 10, &ret, cbcr_branch_on);
 
 	if (ret < 0)
@@ -34,6 +77,68 @@ TEE_Result qcom_clock_enable_cbc(vaddr_t cbcr)
 	return TEE_SUCCESS;
 }
 
+static inline bool pll_locked(uint32_t val)
+{
+	return val & PLL_MODE_LOCK_DET;
+}
+
+TEE_Result qcom_lucidevo_pll_enable(vaddr_t pll_base,
+				    const struct qcom_lucidevo_pll_config *cfg)
+{
+	uint32_t user_val = 0;
+	int ret = 0;
+
+	/* Reg settings: program the static PLL trim/config registers. */
+	io_write32(pll_base + PLL_CONFIG_CTL, cfg->config_ctl);
+	io_write32(pll_base + PLL_CONFIG_CTL_U, cfg->config_ctl_u);
+	io_write32(pll_base + PLL_CONFIG_CTL_U1, cfg->config_ctl_u1);
+	io_write32(pll_base + PLL_USER_CTL, cfg->user_ctl);
+	io_write32(pll_base + PLL_USER_CTL_U, cfg->user_ctl_u);
+
+	/* ConfigPLL: program L value and fractional value. */
+	io_mask32(pll_base + PLL_L_VAL, cfg->l_val, PLL_L_VAL_L_MASK);
+	io_write32(pll_base + PLL_ALPHA_VAL, cfg->alpha_val);
+
+	/* Select fractional format and program the pre-/post-div ratios. */
+	user_val = io_read32(pll_base + PLL_USER_CTL);
+	if (cfg->frac_mode_mn)
+		user_val |= PLL_USER_CTL_FRAC_FORMAT_SEL;
+	else
+		user_val &= ~PLL_USER_CTL_FRAC_FORMAT_SEL;
+
+	user_val &= ~(PLL_USER_CTL_PRE_DIV_MASK |
+		      PLL_USER_CTL_POST_DIV_ODD_MASK |
+		      PLL_USER_CTL_POST_DIV_EVEN_MASK);
+	if (cfg->pre_div >= 1 && cfg->pre_div <= 8)
+		user_val |= SHIFT_U32(cfg->pre_div - 1,
+				      PLL_USER_CTL_PRE_DIV_SHIFT) &
+			    PLL_USER_CTL_PRE_DIV_MASK;
+	io_write32(pll_base + PLL_USER_CTL, user_val);
+
+	/* Always use fine-grained lock detection. */
+	io_setbits32(pll_base + PLL_USER_CTL_U, PLL_USER_CTL_U_FINE_LOCK_DET);
+
+	/* SetCalConfig: program the calibration L value. */
+	io_mask32(pll_base + PLL_L_VAL,
+		  SHIFT_U32(cfg->cal_l_val, PLL_L_VAL_CAL_L_SHIFT),
+		  PLL_L_VAL_CAL_L_MASK);
+
+	/* Enable: select RUN opmode and take the PLL out of reset. */
+	io_write32(pll_base + PLL_OPMODE, PLL_OPMODE_RUN);
+	io_setbits32(pll_base + PLL_MODE, PLL_MODE_RESET_N);
+
+	/* Wait for the PLL to lock. */
+	REG_POLL_TIMEOUT(pll_base + PLL_MODE, 10 * 1000, 10, &ret, pll_locked);
+	if (ret < 0)
+		return TEE_ERROR_TIMEOUT;
+
+	/* Enable PLL outputs and the main output. */
+	io_setbits32(pll_base + PLL_MODE, PLL_MODE_OUTCTRL);
+	io_setbits32(pll_base + PLL_USER_CTL, PLL_USER_CTL_PLLOUT_MAIN_EN);
+
+	return TEE_SUCCESS;
+}
+
 TEE_Result qcom_clock_set_rate(vaddr_t cfg_rcgr, vaddr_t cmd_rcgr,
 			       uint32_t cfg_value)
 {
@@ -53,8 +158,11 @@ TEE_Result qcom_clock_enable(enum qcom_clk_group group)
 {
 	switch (group) {
 	case QCOM_CLKS_TURING:
+	case QCOM_CLKS_TURING1:
 	case QCOM_CLKS_LPASS:
 	case QCOM_CLKS_WPSS:
+	case QCOM_CLKS_GPDSP0:
+	case QCOM_CLKS_GPDSP1:
 		return qcom_clock_enable_pas(group);
 	default:
 		EMSG("Unsupported clock group %d\n", group);