feature: accelerate line-buffered rolled conv and depthwise on CMSIS-NN and ESP-NN

[asteinh]

Summary

Line-buffered chains roll their overlap rows across tiles, but every rolled tile fell back to
s8_ref on the accelerated backends (the tigris_accel_try_s8_ref guard). This teaches the
CMSIS-NN and ESP-NN Conv/Depthwise adapters to honor the roll offsets, so a rolled chain
accelerates. Second substep of Phase 1.5 (native tile-contract acceleration).

Change

• tigris_accel_try_s8_ref (tigris_kernels_s8.c): a rolled tile's conv/depthwise now proceeds
  to the vendor adapter; a rolled non-conv/depthwise op still routes to s8_ref, and every
  2D-width tile still routes to s8_ref (deferred to 1.5c).
• adapt_conv2d / adapt_depthwise_conv2d in both the CMSIS-NN and ESP-NN adapters: fold the
  roll into pointer offsets - Y += out_row_start rows, X += (out_row_start*stride - in_row_start) rows, IH -= that delta - mirroring the oh_g / ih index math in
  kern_conv2d_s8. For a spatial op the executor sets in_row_start = 0, so the delta is
  out_row_start*stride.
• test_accel_routing.c: a rolled conv/depthwise routes to the adapter; a rolled
  non-conv/depthwise (max-pool) still routes to reference.

Testing

• Routing unit tests: 46 passed.
• Host CMSIS-NN differential on a line-buffered rolled chain (a 2-conv chain, 6 tiles, 8 roll
  events; instrumentation confirmed the CMSIS adapter roll block executes with
  out_row_start=2/delta=2): max_abs_diff=0 (bit-exact) vs the reference dispatcher through
  the executor. The 1.5a plain-height conv/depthwise differentials still pass.
• Full runtime unit suite green; stack-usage gate passes; MISRA baseline regenerated locally
  (+1 advisory finding, 0 correctness).
• ESP-NN acceleration is Xtensa-only, so its roll path mirrors the host-verified CMSIS logic
  exactly and is validated on-device (SiliconRig) separately, as in 1.5a.

Follow-up

The persistent CI differential (a rolled-chain case in tigris-bench host-validation + a
core-versions.json re-pin) lands after this merges, per the standard bench re-pin flow.