Refactor/interface naming#16
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Change run_sim.sh from using grep to check each module for compilation errors or tb errors, to checking the exit status from the tb. Removed now-unused -o pipefail from flags . In order to see entire tb run before exiting, added an error counter to each tb, read with `$fatal` at the end to produce exit status.
…g_tb Icarus Verilog 12.0 can't force an entire unpacked array or a single word of one, so IB/OB/size are seeded with plain hierarchical assignments instead. Addresses review comment from prof Rovinski on PR realise-lab#14.
Added documentation headers to all modules, matching bram_tree.sv
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depends on PR #15 |
the restored comment contained a reference to an o_ready port that does not exist in the bram_tree.sv module. The copied comment on bram_tree_pipelined.sv also had this mistake. Both removed, though they describe something that could be quite useful...
src files wip - my bash script didnt do quite as well on those
had to update the comments as well and fix some script failure by hand
…orm across modules
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Replaces o_full/o_empty we want o_write_ready/o_read_ready
Renamed ports across all tbs and srcs, inverted assignments, and updated header and inline comments
also unified i_CLK and i_RSTn port naming in preparation for potential testbench standardization