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Merged
aniketEng merged 6 commits into from
Mar 6, 2026
Merged

More thorough linting #53

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e67e919
Drove the outputs of the lint_stubs
aniketEng Feb 16, 2026
6597601
Updated 2FF synchronizer to support both sync and async resets
aniketEng Feb 16, 2026
8353447
Made linting stricter checking against all warnings
aniketEng Feb 16, 2026
5c9b8b0
Cleaned up linting
aniketEng Feb 16, 2026
5d36777
Fixing the scorebaord to accomodate new clock cycles introduced in th…
rojalinm Feb 27, 2026
654305d
Updated lint_stubs interfaces
aniketEng Mar 2, 2026
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2 changes: 1 addition & 1 deletion Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -281,7 +281,7 @@ distclean: clean

verilator_lint:
@$(MAKE) check_verilator
@verilator --lint-only -sv -Isrc $(LINT_FILES) lint_waivers.vlt --top QECIPHY
@verilator --lint-only -sv -Wall lint_waivers.vlt -Isrc $(LINT_FILES) --top QECIPHY

verible_format:
@$(MAKE) check_verible
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28 changes: 21 additions & 7 deletions lib/riv_synchronizer_2ff/src/riv_synchronizer_2ff.sv
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Expand Up @@ -5,7 +5,9 @@
`ifndef RIV_SYNCHRONIZER_2FF_SV
`define RIV_SYNCHRONIZER_2FF_SV

module riv_synchronizer_2ff (
module riv_synchronizer_2ff #(
parameter string RESET_TYPE = "SYNC"
Comment thread
aniketEng marked this conversation as resolved.
) (
input logic src_in, // signal to be synchronised
input logic dst_clk, // destination clock domain
input logic dst_rst_n, // destination domain active low reset
Expand All @@ -21,13 +23,25 @@ module riv_synchronizer_2ff (
// Logic
// -------------------------------------------------------------

always_ff @(posedge dst_clk or negedge dst_rst_n) begin
if (~dst_rst_n) begin
sync_stage_sf <= 2'h0;
end else begin
sync_stage_sf <= {sync_stage_sf[0], src_in};
generate
if (RESET_TYPE == "ASYNC") begin : gen_synchronizer_with_async_reset
always_ff @(posedge dst_clk or negedge dst_rst_n) begin
if (!dst_rst_n) begin
sync_stage_sf <= 2'h0;
end else begin
sync_stage_sf <= {sync_stage_sf[0], src_in};
end
end
end else begin : gen_synchronizer_with_sync_reset
always_ff @(posedge dst_clk) begin
if (!dst_rst_n) begin
sync_stage_sf <= 2'h0;
end else begin
sync_stage_sf <= {sync_stage_sf[0], src_in};
end
end
end
end
endgenerate

assign dst_out = sync_stage_sf[1];

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2 changes: 2 additions & 0 deletions lint_stubs/BUFG_GT.sv
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Expand Up @@ -20,4 +20,6 @@ module BUFG_GT (
output O
);

assign O = '0;

endmodule
10 changes: 10 additions & 0 deletions lint_stubs/GTXE2_COMMON.sv
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Expand Up @@ -68,4 +68,14 @@ module GTXE2_COMMON #(
input logic RCALENB
);

assign DRPDO = '0;
assign DRPRDY = '0;
assign QPLLDMONITOR = '0;
assign QPLLOUTCLK = '0;
assign QPLLOUTREFCLK = '0;
assign REFCLKOUTMONITOR = '0;
assign QPLLFBCLKLOST = '0;
assign QPLLLOCK = '0;
assign QPLLREFCLKLOST = '0;

endmodule
4 changes: 4 additions & 0 deletions lint_stubs/qeciphy_clk_mmcm.sv
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Expand Up @@ -18,4 +18,8 @@ module qeciphy_clk_mmcm (
input clk_in
);

assign clk_out_2x = '0;
assign clk_out = '0;
assign input_clk_stopped = '0;

endmodule
112 changes: 67 additions & 45 deletions lint_stubs/qeciphy_gth_transceiver.sv
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Expand Up @@ -11,51 +11,73 @@
// -----------------------------------------------------------------------------

module qeciphy_gth_transceiver (
input gtwiz_userclk_tx_active_in,
input gtwiz_userclk_rx_active_in,
input gtwiz_reset_clk_freerun_in,
input gtwiz_reset_all_in,
input gtwiz_reset_tx_pll_and_datapath_in,
input gtwiz_reset_tx_datapath_in,
input gtwiz_reset_rx_pll_and_datapath_in,
input gtwiz_reset_rx_datapath_in,
output gtwiz_reset_rx_cdr_stable_out,
output gtwiz_reset_tx_done_out,
output gtwiz_reset_rx_done_out,
input [31:0] gtwiz_userdata_tx_in,
output [31:0] gtwiz_userdata_rx_out,
input gtrefclk00_in,
output qpll0outclk_out,
output qpll0lock_out,
output qpll0outrefclk_out,
input gthrxn_in,
input gthrxp_in,
input rx8b10ben_in,
input rxusrclk_in,
input rxusrclk2_in,
input tx8b10ben_in,
input [15:0] txctrl0_in,
input [15:0] txctrl1_in,
input [7:0] txctrl2_in,
input txusrclk_in,
input txusrclk2_in,
output gtpowergood_out,
output gthtxn_out,
output gthtxp_out,
output [15:0] rxctrl0_out,
output [15:0] rxctrl1_out,
output [7:0] rxctrl2_out,
output [7:0] rxctrl3_out,
output rxoutclk_out,
output rxpmaresetdone_out,
output txoutclk_out,
output txpmaresetdone_out,
input rxcommadeten_in,
input rxpcommaalignen_in,
input rxmcommaalignen_in,
output rxbyteisaligned_out,
output rxbyterealign_out,
output rxcommadet_out
input logic gtwiz_userclk_tx_active_in,
input logic gtwiz_userclk_rx_active_in,
input logic gtwiz_reset_clk_freerun_in,
input logic gtwiz_reset_all_in,
input logic gtwiz_reset_tx_pll_and_datapath_in,
input logic gtwiz_reset_tx_datapath_in,
input logic gtwiz_reset_rx_pll_and_datapath_in,
input logic gtwiz_reset_rx_datapath_in,
output logic gtwiz_reset_rx_cdr_stable_out,
output logic gtwiz_reset_tx_done_out,
output logic gtwiz_reset_rx_done_out,
input logic [31:0] gtwiz_userdata_tx_in,
output logic [31:0] gtwiz_userdata_rx_out,
input logic gtrefclk00_in,
output logic qpll0outclk_out,
output logic qpll0lock_out,
output logic qpll0outrefclk_out,
input logic gthrxn_in,
input logic gthrxp_in,
input logic rx8b10ben_in,
input logic rxusrclk_in,
input logic rxusrclk2_in,
input logic tx8b10ben_in,
input logic [15:0] txctrl0_in,
input logic [15:0] txctrl1_in,
input logic [7:0] txctrl2_in,
input logic txusrclk_in,
input logic txusrclk2_in,
output logic gtpowergood_out,
output logic gthtxn_out,
output logic gthtxp_out,
output logic [15:0] rxctrl0_out,
output logic [15:0] rxctrl1_out,
output logic [7:0] rxctrl2_out,
output logic [7:0] rxctrl3_out,
output logic rxoutclk_out,
output logic rxpmaresetdone_out,
output logic txoutclk_out,
output logic txpmaresetdone_out,
input logic rxcommadeten_in,
input logic rxpcommaalignen_in,
input logic rxmcommaalignen_in,
output logic rxbyteisaligned_out,
output logic rxbyterealign_out,
output logic rxcommadet_out
);

assign gtwiz_reset_rx_cdr_stable_out = '0;
assign gtwiz_reset_tx_done_out = '0;
assign gtwiz_reset_rx_done_out = '0;
assign gtwiz_userdata_rx_out = '0;
assign qpll0outclk_out = '0;
assign qpll0lock_out = '0;
assign qpll0outrefclk_out = '0;
assign gtpowergood_out = '0;
assign gthtxn_out = '0;
assign gthtxp_out = '0;
assign rxctrl0_out = '0;
assign rxctrl1_out = '0;
assign rxctrl2_out = '0;
assign rxctrl3_out = '0;
assign rxoutclk_out = '0;
assign rxpmaresetdone_out = '0;
assign txoutclk_out = '0;
assign txpmaresetdone_out = '0;
assign rxbyteisaligned_out = '0;
assign rxbyterealign_out = '0;
assign rxcommadet_out = '0;

endmodule
143 changes: 84 additions & 59 deletions lint_stubs/qeciphy_gtx_transceiver.sv
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Expand Up @@ -11,65 +11,90 @@
// -----------------------------------------------------------------------------

module qeciphy_gtx_transceiver (
input sysclk_in,
input soft_reset_tx_in,
input soft_reset_rx_in,
input dont_reset_on_data_error_in,
output gt0_tx_fsm_reset_done_out,
output gt0_rx_fsm_reset_done_out,
input gt0_data_valid_in,
input [ 8:0] gt0_drpaddr_in,
input gt0_drpclk_in,
input [15:0] gt0_drpdi_in,
output [15:0] gt0_drpdo_out,
input gt0_drpen_in,
output gt0_drprdy_out,
input gt0_drpwe_in,
output [ 7:0] gt0_dmonitorout_out,
input [ 2:0] gt0_loopback_in,
input gt0_eyescanreset_in,
input gt0_rxuserrdy_in,
output gt0_eyescandataerror_out,
input gt0_eyescantrigger_in,
input gt0_rxusrclk_in,
input gt0_rxusrclk2_in,
output [31:0] gt0_rxdata_out,
output [ 3:0] gt0_rxdisperr_out,
output [ 3:0] gt0_rxnotintable_out,
input gt0_gtxrxp_in,
input gt0_gtxrxn_in,
input gt0_rxdfelpmreset_in,
output [ 6:0] gt0_rxmonitorout_out,
input [ 1:0] gt0_rxmonitorsel_in,
output gt0_rxoutclk_out,
output gt0_rxoutclkfabric_out,
input gt0_gtrxreset_in,
input gt0_rxpmareset_in,
output [ 3:0] gt0_rxcharisk_out,
output gt0_rxresetdone_out,
input gt0_gttxreset_in,
input gt0_txuserrdy_in,
input gt0_txusrclk_in,
input gt0_txusrclk2_in,
input [31:0] gt0_txdata_in,
output gt0_gtxtxn_out,
output gt0_gtxtxp_out,
output gt0_txoutclk_out,
output gt0_txoutclkfabric_out,
output gt0_txoutclkpcs_out,
input [ 3:0] gt0_txcharisk_in,
input gt0_txpmareset_in,
output gt0_txresetdone_out,
input gt0_qplllock_in,
input gt0_qpllrefclklost_in,
output gt0_qpllreset_out,
input gt0_qplloutclk_in,
input gt0_qplloutrefclk_in,
input gt0_rxpcommaalignen_in,
input gt0_rxmcommaalignen_in,
output gt0_rxbyteisaligned_out,
output gt0_rxbyterealign_out,
output gt0_rxcommadet_out
input logic sysclk_in,
input logic soft_reset_tx_in,
input logic soft_reset_rx_in,
input logic dont_reset_on_data_error_in,
output logic gt0_tx_fsm_reset_done_out,
output logic gt0_rx_fsm_reset_done_out,
input logic gt0_data_valid_in,
input logic [ 8:0] gt0_drpaddr_in,
input logic gt0_drpclk_in,
input logic [15:0] gt0_drpdi_in,
output logic [15:0] gt0_drpdo_out,
input logic gt0_drpen_in,
output logic gt0_drprdy_out,
input logic gt0_drpwe_in,
output logic [ 7:0] gt0_dmonitorout_out,
input logic [ 2:0] gt0_loopback_in,
input logic gt0_eyescanreset_in,
input logic gt0_rxuserrdy_in,
output logic gt0_eyescandataerror_out,
input logic gt0_eyescantrigger_in,
input logic gt0_rxusrclk_in,
input logic gt0_rxusrclk2_in,
output logic [31:0] gt0_rxdata_out,
output logic [ 3:0] gt0_rxdisperr_out,
output logic [ 3:0] gt0_rxnotintable_out,
input logic gt0_gtxrxp_in,
input logic gt0_gtxrxn_in,
input logic gt0_rxdfelpmreset_in,
output logic [ 6:0] gt0_rxmonitorout_out,
input logic [ 1:0] gt0_rxmonitorsel_in,
output logic gt0_rxoutclk_out,
output logic gt0_rxoutclkfabric_out,
input logic gt0_gtrxreset_in,
input logic gt0_rxpmareset_in,
output logic [ 3:0] gt0_rxcharisk_out,
output logic gt0_rxresetdone_out,
input logic gt0_gttxreset_in,
input logic gt0_txuserrdy_in,
input logic gt0_txusrclk_in,
input logic gt0_txusrclk2_in,
input logic [31:0] gt0_txdata_in,
output logic gt0_gtxtxn_out,
output logic gt0_gtxtxp_out,
output logic gt0_txoutclk_out,
output logic gt0_txoutclkfabric_out,
output logic gt0_txoutclkpcs_out,
input logic [ 3:0] gt0_txcharisk_in,
input logic gt0_txpmareset_in,
output logic gt0_txresetdone_out,
input logic gt0_qplllock_in,
input logic gt0_qpllrefclklost_in,
output logic gt0_qpllreset_out,
input logic gt0_qplloutclk_in,
input logic gt0_qplloutrefclk_in,
input logic gt0_rxpcommaalignen_in,
input logic gt0_rxmcommaalignen_in,
output logic gt0_rxbyteisaligned_out,
output logic gt0_rxbyterealign_out,
output logic gt0_rxcommadet_out
);

assign gt0_tx_fsm_reset_done_out = '0;
assign gt0_rx_fsm_reset_done_out = '0;
assign gt0_drpdo_out = '0;
assign gt0_drprdy_out = '0;
assign gt0_dmonitorout_out = '0;
assign gt0_eyescandataerror_out = '0;
assign gt0_rxdata_out = '0;
assign gt0_rxdisperr_out = '0;
assign gt0_rxnotintable_out = '0;
assign gt0_rxmonitorout_out = '0;
assign gt0_rxoutclk_out = '0;
assign gt0_rxoutclkfabric_out = '0;
assign gt0_rxcharisk_out = '0;
assign gt0_rxresetdone_out = '0;
assign gt0_gtxtxn_out = '0;
assign gt0_gtxtxp_out = '0;
assign gt0_txoutclk_out = '0;
assign gt0_txoutclkfabric_out = '0;
assign gt0_txoutclkpcs_out = '0;
assign gt0_txresetdone_out = '0;
assign gt0_qpllreset_out = '0;
assign gt0_rxbyteisaligned_out = '0;
assign gt0_rxbyterealign_out = '0;
assign gt0_rxcommadet_out = '0;

endmodule
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