skywater130

Here are 7 public repositories matching this topic...

bazx-bit / caravel-direct-rf

Cognitive Direct-RF Sampling Transceiver: Massively pipelined SDR DSP baseband engine hardened on SkyWater 130nm for Efabless Caravel OpenMPW tapeout. 100-phase SystemVerilog RTL, OpenLane ASIC signoff, and 100% regression verified.

asic dsp sdr fft transceiver systemverilog digital-signal-processing viterbi caravel wishbone qam hardware-verification tapeout efabless openlane open-source-silicon skywater130 rf-dsp

Updated Oct 11, 2026
Verilog

S-SUJAN-S / rtl2gds

Star

🚀 SiliconFlow-AI: Autonomous RTL-to-GDSII Physical Design Framework uniting LLM Agents with native EDA engines (Verilator, Yosys, OpenSTA, OpenLane) on SkyWater 130nm PDK.

asic eda verilog vlsi yosys gdsii electronic-design-automation physical-design openroad openlane llm-agents hardware-ai rtl-to-gdsii skywater130

Updated Oct 10, 2026
Python

ishwar170695 / silicon-as-distributed-system

Star

Silicon as a Distributed System: Closing the Cross-Layer Loop from Spatial Manufacturing Defects to Wafer-Level Economics

distributed-systems fault-tolerance computer-architecture microarchitecture open-source-hardware network-on-chip spatial-computing hardware-accelerator ai-accelerators semiconductor-yield wafer-scale skywater130

Updated Sep 4, 2026
Python

AmberVats / l1-cache-controller

Star

32KB 4-Way Set-Associative L1 Cache Controller with Non-Blocking MSHR, Tree-PLRU, and AXI4 Refills targeting SkyWater 130nm.

asic systemverilog yosys axi4 cache-controller l1-cache mshr pseudo-lru skywater130

Updated Aug 19, 2026
SystemVerilog

timfromhcs / tt-universal-edge-ai-asic

Star

Universal Edge AI ASIC: Open-Source Silicon Accelerator for LLMs (llama.cpp GGUF Q4_K/IQ) & Diffusion DiT (Flux, SDXL) in SkyWater SKY130 130nm CMOS.

Updated Aug 27, 2026
Python

eggdan6666 / Auto-Compute-RTL

Star

A Dual-Loop Self-Healing Systolic Array with Time-Multiplexed Spare Column for Online Zero-Masking and Hot-Swapping in DNN Accelerators

asic deep-learning fault-tolerance systemverilog self-healing bist abft systolic-array skywater130 dnn-accelerator

Updated Oct 15, 2026
SystemVerilog

Ahmed-Ashoor / 256-Point-SDF-FFT-RTL-to-GDSII

Star

A fully pipelined 256-point FFT based on the radix-2 Decimation-in-Frequency (DIF) Single-Delay-Feedback (SDF) architecture. The project covers the complete digital design flow: algorithm modeling on MATLAB, RTL design, UVM style verification, and physical implementation on the open-source SkyWater 130nm PDK using OpenLane.

asic matlab verification verilog systemverilog asic-design rtl-design digital-ic openlane digital-ic-design skywater130

Updated Oct 8, 2026
SystemVerilog

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