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Add DragonBench fan-characterization experiment profile - #8
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Platform-neutral core for a bench-only FAN_PWM_HOLD workload: parameter validation (pwm_hz 10..50000, sink_duty_pct 0..100 in 0.1 steps, explicit duration), LEDC duty planning, tach edge frequency, and RPM only from an explicitly configured PPR. db_fan_hold() drives hardware through a small ops seam and releases the stimulus line on its single exit path: run end, abort, and every failure. The workload is registered in every build but supported only when CONFIG_DB_FAN_FIXTURE is set, so normal profiles report and reject it. Host tests cover both profiles, release on boot/end/abort/error, unknown PPR, and the phase_end event-size budget. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
CONFIG_DB_FAN_FIXTURE (off in every normal profile) compiles an LEDC stimulus that drives only the gate of an external open-drain stage and a PCNT falling-edge tach counter. Gate GPIO, gate sink level, and tach GPIO have no defaults: an unconfigured fixture build stops with an #error per missing setting, and reserved or colliding pins also fail the build. A non-zero PPR requires an evidence reference. The gate is released first in app_main, before every hold, on every hold exit, and from a shutdown handler. Release moves the pad back to a plain GPIO output and reads it back. heater_capability and fan_control_capability stay false in every build. The new bench_stimulus object and landing-page chip report the fixture separately from product control. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
fan-sweep runs one FAN_PWM_HOLD per sink-duty step in up, down, up-down, or down-up order and rewrites a JSON results file after every step. It refuses a device that does not report a fan-fixture build, stops at the first non-pass step, and aborts the active run on timeout, refusal, or Ctrl-C. Sweep logic lives only on the host. HTTP error responses now surface the device's error message. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
CI builds the normal profiles and fails if their ELF links any LEDC, PCNT, or fan-fixture symbol. It checks that the fixture overlay without wiring refuses to build, and runs the native tests as both profiles. OpenAPI, README, and architecture docs now describe the bench stimulus without implying product fan control. docs/FAN_FIXTURE.md records the electrical model, the release guarantees, the metrics semantics, known limitations, and the wiring decisions still open. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
db_fan_pwm_plan() could hand LEDC duty == 2^duty_resolution for 100 % sink, which ESP-IDF 5.3.5 documents as overflowing the ESP32-S3 duty counter. The stimulus is now one of three explicit modes: 0 % holds the gate at the release level, 100 % holds it at the sink level, and only values strictly between use LEDC, with the compare value guaranteed to be 1..2^bits-1. sink_duty_pct keeps its meaning: the fraction of time the external stage sinks the fan PWM line. Events name the mode. The hardware seam is now pad-level (drive_static, start_pwm). The common layer decides which gate level sinks from gate_sink_level, so native tests cover 0 %, PWM, and 100 % for both stage polarities, including the sink fraction the modeled line actually sees. Tach readiness is checked after the pre-release and before any actuation, and the run is refused with tach_unavailable if capture is not available. The counter clear still happens right before the window opens. Release still runs on every exit path. The phase_end worst case outgrew the 512-byte event slot, so the slot is now 640 bytes. emit_event no longer stores a cut-off JSON line: an oversized event drops parameters/metrics and is marked truncated. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
DragonBench images are now one board profile plus one experiment profile, chosen by the mutually exclusive Kconfig choice DB_EXPERIMENT_PROFILE: baseline (default, explicit in sdkconfig.defaults) or fan-characterization. This replaces the independent DB_FAN_FIXTURE flag, so profiles cannot drift into combinable feature switches. - db_experiment.h is the only place that reads the choice; code is compiled under DB_EXPERIMENT_* and the profile name comes from there. - sdkconfig.defaults.fan-characterization selects the profile; wiring lives in the untracked sdkconfig.fan-characterization.local and still has no defaults. The fixture options exist only inside the profile. - fan_fixture.[ch] becomes fan_characterization.[ch]. - /api/v1/device reports experiment_profile, and fan-sweep requires fan-characterization instead of inferring it from capabilities. - ci/build-esp32s3.sh takes <board> [experiment] [--expect-refusal] and checks that every other experiment's code is absent from each ELF. test_experiment_profiles.py enforces the pattern: one choice, one name, one overlay, and one CI entry per profile, and no CONFIG_DB_EXPERIMENT_ reads outside db_experiment.h. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
…urces /api/v1/device now states what produced an artifact without inference: board_profile, experiment_profile, device_id, and a build object with firmware_version, git_sha, source_tree, and esp_idf. The boot event carries the same image identity so a serial log alone names what ran. build_provenance.cmake runs on every build and rewrites db_build_provenance.h only when it changes, so incremental builds never report a stale revision. It records only what git establishes: no git, no work tree, or a failed query gives git_sha null and source_tree unknown. Untracked, non-ignored files count as dirty. idf-build.log is now ignored so CI's own log does not dirty the tree. measurement_authority: external_bench_equipment stopped being true once PCNT counted tach edges. It is replaced by measurement_provenance, which maps each quantity to dut.<peripheral>, derived.<rule>, or external. fan_speed is external unless a PPR was configured with evidence. The fan profile also lists fan_tach_edges in /api/v1/sensors, and CLI export includes /api/v1/device. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
docs/EXPERIMENT_PROFILES.md defines the platform pattern: one board profile plus one mutually exclusive experiment profile per image, what every profile reports (identity, build revision, measurement provenance), and the rules for adding one. docs/FAN_CHARACTERIZATION.md (was FAN_FIXTURE.md) now covers the static 0 % / 100 % endpoints and why LEDC never sees 2^duty_resolution, tach readiness before actuation, the hold sequence, the stimulus field, the new fixture_error values, and identity/provenance. README, ARCHITECTURE, BENCH_WORKFLOW, and the native-test README follow the new names. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
Hosted CI built only baseline images and the fan profile's expected refusal, so the real fan-characterization backend (static gate drive, LEDC, PCNT) was never compiled by GitHub Actions. A new matrix job builds it for tinys3d and n8r8 with the same ci/build-esp32s3.sh checks: zero warnings, and the fan code must link. Each entry writes sdkconfig.fan-characterization.local inside the runner workspace only (the file stays git-ignored). The GPIO values are CI compile fixtures: not DragonBench reference wiring, not JumpJet wiring, and not hardware recommendations. Each set passes the existing reserved/conflict guards for its board. The boards use opposite gate sink levels so both stage polarities compile, and PPR stays unknown. No guard is relaxed. test_experiment_profiles now requires every non-baseline experiment to have at least one configured hosted ESP-IDF build that writes its local wiring overlay, so a future profile cannot ship with refusal-only CI. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
Adds the n16r8 board profile (ESP32-S3-WROOM-1 marked MCN16R8, 16 MB flash, 8 MB Octal PSRAM, Lonely Binary carrier) as sdkconfig.defaults.n16r8 layered on the shared defaults. It reports target esp32s3-n16r8, sets 16 MB flash, and inherits Octal PSRAM at 80 MHz and no RF switch. partitions.csv is unchanged and ends below 8 MB; the upper flash is intentionally unused. CONFIG_DB_BOARD_RESERVED_GPIO names a GPIO the board wires to an onboard peripheral. The N16R8 sets it to 48 (onboard RGB LED), and the fan-characterization pin guards refuse it as gate or tach. Other boards leave it at -1, so GPIO48 is not reserved globally. Board overlays are now identified explicitly from the build script's board profiles instead of by filename exception, so an overlay is either a board or an experiment and board overlays never select an experiment. Host tests run the real fixture pin guards through the C preprocessor for each board. CI builds n16r8 in the baseline and configured fan-characterization matrices (compile fixture GPIO6 gate, sink level 1, GPIO7 tach, PPR 0) and now also verifies each board's flash size and board-reserved GPIO. Build-validated only; physical flash and boot on the N16R8 are pending. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JqMRE3TFJJAGiE368AG91j
Replaces the one-off DB_BOARD_RESERVED_GPIO with board-owned status RGB resources: CONFIG_DB_STATUS_RGB_GPIO, CONFIG_DB_STATUS_RGB_POWER_GPIO and CONFIG_DB_STATUS_RGB_POWER_ACTIVE_LEVEL, set per board from its schematic or silkscreen: - N8R8 (YD-ESP32-S3 V1.4): WS2812B data GPIO48, 5 V supply, no power GPIO - N16R8 (Lonely Binary, RGB@IO48): data GPIO48, no power GPIO - TinyS3[D] (Rev D-P1): WS2812B data GPIO18, VDD from GPIO17 (high on) The fan-characterization pin guards reject the data and power pins as gate or tach, alongside the existing RF-switch and other exclusions. DragonBench drives the LED itself as a status light through the RMT bytes encoder: off from boot until the ready event, solid dim green while ready and idle, and off, under state_lock, before a run's phase_start until that run ends. It returns to green only after a passing run. The policy is a pure function, db_status_ready(), shared by every experiment profile and tested natively; on TinyS3[D] off also removes LED power. Build- and test-validated only; no LED has been observed on hardware. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JqMRE3TFJJAGiE368AG91j
Lonely Binary's own GPIO map for the ESP32-S3 Gold Edition confirms the N16R8 facts DragonBench relies on: GPIO48 is restricted and carries the RGB@IO48 LED beside an RGB solder pad, GPIO35-37 are unusable, the strapping, USB and console pins are restricted, and GPIO6/7 are plain GPIO. It also labels the two USB-C connectors UART and USB. No firmware change: the existing pin guards already reject every pin the map restricts. The LED part and the RGB pad state remain unconfirmed. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JqMRE3TFJJAGiE368AG91j
Dan confirmed the N8R8 is the original VCC-GND YD-ESP32-S3, not a Lonely Binary board. Comparing VCC-GND's pin table and schematic V1.4 with Lonely Binary's GPIO map, the GPIOs DragonBench uses or rejects agree on both carriers: GPIO6/7 plain GPIO, GPIO48 the RGB LED, GPIO35-37 taken by Octal PSRAM, GPIO19/20 native USB, GPIO43/44 UART0, and 0/3/45/46 strapping. The docs record that equivalence and keep the carrier differences separate: flash size, USB-UART bridge, RGB electrical wiring, YD-only parts on already-rejected pins, and connector labels. No firmware or config change. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01JqMRE3TFJJAGiE368AG91j
The n16r8/baseline image from 153c6d1 (ESP-IDF 5.3.5, clean tree) was flashed to and exercised on one Lonely Binary MCN16R8 board, with no fixture, fan, GPIO6/7 wiring or 24 V connected. Confirmed on the board: identity and build provenance, 16 MB flash, the 8 MB AP gen-3 PSRAM via ESP-IDF's Octal driver with the boot memory test passing, clean boots to ready, RESET and bridge-RTS resets, flashing through both USB-C connectors (UART bridge 1A86:7522, native USB 303A:1001), the status LED dark-then-green sequence (visual), the access point, mDNS, and the read-only API. Still unvalidated: station mode, host-driven reset over native USB, the bridge and LED parts, the RGB pad, workloads, the fan-characterization image, fixture wiring, and fan and electrical characterization.
The n16r8/fan-characterization image from b90e713 (ESP-IDF 5.3.5, clean tree; gate GPIO6, sink level 1, tach GPIO7, PPR 0) was flashed over the UART connector and run with only a DMM on GPIO6: no fixture, stage, fan or 24 V, and GPIO7 unconnected. Observed: clean boot with the designed profile banner, correct identity, FAN_PWM_HOLD available, heater and fan control false. GPIO6 measured 0 V at idle, after runs and after reset; 0 V during a 0% hold and 3.26 V during a 100% hold. Holds passed with ordered phase_start, phase_end and run_complete events, and the status LED was off during each run. Still unvalidated: the PWM waveform between the endpoints (pending a logic analyzer), the shutdown handler, the fixture and external stage, real tach capture, PPR, and fan and electrical characterization.
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Navigate logical layers of code changes, visualize relationships, and explore their blast radius. No actionable comments were generated in the recent review. 🎉 ℹ️ Recent review info⚙️ Run configurationConfiguration used: Organization UI Review profile: ASSERTIVE Plan: Advanced Run ID: 📒 Files selected for processing (1)
Included review availability: This review used your included allowance. Your plan provides up to 10 included reviews per hour; 5 remain after this review. 📝 WalkthroughWalkthroughThis pull request adds ESP32-S3 board and experiment profiles, a profile-gated fan-characterization workload, and a host-side duty sweep. It also adds device and build metadata, status RGB behavior, protocol descriptions, documentation, and tests. ChangesFan Characterization
Priority: ➖ Normal Estimated code review effort: 4 (Complex) | ~60 minutes Change: Feature Sequence Diagram(s)sequenceDiagram
participant Sweep as fan_sweep
participant Client
participant Device as /api/v1/device
participant Runs as /api/v1/runs
participant Events as /api/v1/events
Sweep->>Client: Read device profile
Client->>Device: Request device identity
Device-->>Client: Return experiment profile and fixture metadata
Sweep->>Client: Submit one FAN_PWM_HOLD per planned duty
Client->>Runs: Create run and poll run state
Runs-->>Client: Return run status and result
Sweep->>Client: Collect events for completed run
Client->>Events: Request run events
Events-->>Client: Return phase data and metrics
Sweep->>Sweep: Update partial JSON report
Merge Risk: ⚪ Minimal · up to The documentation clearly distinguishes provisional fixture wiring from validated hardware behavior; no material merge risk remains. Architecture SummaryArchitecture risk: 🔵 Low · up to The change affects 12 systems. Changed systems: Architecture concerns Review detailsSystems and components
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🚥 Pre-merge checks | ✅ 4 | ❌ 1❌ Failed checks (1 warning)
✅ Passed checks (4 passed)
Full details: Docstring CoverageExplanation Docstring coverage is 8.59% which is insufficient. The required threshold is 80.00%. Docstring coverage is scoped to functions touched by this diff. Analyzed 198 functions across 20 files. (1 skipped: 1 unsupported.)
✨ Finishing Touches🧪 Generate unit tests (beta)
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Inline comments:
Review comments at @docs/FAN_CHARACTERIZATION.md:
- Around line 17-18: Update the wiring-status text and board-choice entry in
FAN_CHARACTERIZATION to identify the N16R8 Rev 0 wiring as provisional and link
to TARGET_N16R8. Keep the stage, tach-circuit, and PPR open items unchanged.
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.github/workflows/ci.yml.gitignoreREADME.mdci/build-esp32s3.shcli/dragonbench/main.pydocs/ARCHITECTURE.mddocs/BENCH_WORKFLOW.mddocs/EXPERIMENT_PROFILES.mddocs/FAN_CHARACTERIZATION.mddocs/TARGET_ESP32S3.mddocs/TARGET_N16R8.mddocs/TARGET_TINYS3D.mdfirmware/common/CMakeLists.txtfirmware/common/db_fan.cfirmware/common/db_run.cfirmware/common/include/db_experiment.hfirmware/common/include/db_fan.hfirmware/common/include/db_run.hfirmware/targets/esp32s3/main/CMakeLists.txtfirmware/targets/esp32s3/main/Kconfig.projbuildfirmware/targets/esp32s3/main/build_provenance.cmakefirmware/targets/esp32s3/main/fan_characterization.cfirmware/targets/esp32s3/main/fan_characterization.hfirmware/targets/esp32s3/main/main.cfirmware/targets/esp32s3/main/status_rgb.cfirmware/targets/esp32s3/main/status_rgb.hprotocol/event.schema.jsonprotocol/openapi.yamlsdkconfig.defaultssdkconfig.defaults.fan-characterizationsdkconfig.defaults.n16r8sdkconfig.defaults.tinys3dtests/native/README.mdtests/native/test_db_fan.ctests/native/test_db_run.ctests/test_board_profiles.pytests/test_experiment_profiles.pytests/test_fan_characterization_contract.pytests/test_fan_sweep.pytests/test_identity_provenance.pytests/test_status_rgb.pyweb/index.html
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FAN_CHARACTERIZATION.md still said the wiring was undefined and listed the fixture board and gate/tach GPIOs as open, although TARGET_N16R8.md already records the provisional Rev 0 wiring: N16R8, GPIO6 gate with CONFIG_DB_FAN_GATE_SINK_LEVEL=1, GPIO7 conditioned tach input, and PPR still 0 (unknown). The no-load smoke test used those pins. The status paragraph and Open items now name that wiring as provisional bench-fixture assignments, not JumpJet product GPIOs, and link to TARGET_N16R8.md. No complete fixture has been built or connected: the physical stage, tach conditioning, fan electrical limits, glitch filter and PPR remain open. Documentation only.
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The fixture still described its controller wiring as an N8R8 breakout overlay, with reasoning about a CH343P board and the ESP32-S3-DevKitC-1. The provisional Rev 0 controller is now the N16R8 on Lonely Binary's carrier, as PR #8's docs/TARGET_N16R8.md records: GPIO6 gate, CONFIG_DB_FAN_GATE_SINK_LEVEL=1, GPIO7 tach, PPR 0 (unknown). The J1 mapping and sdkconfig lines are unchanged; only the board they belong to and the reasoning about it change. The README overlay table, the BRINGUP flash step and the sheet note now name the N16R8, and the README gives its build overlay chain. The DevKitC/CH343P paragraph is replaced by what Lonely Binary's map shows for GPIO6/7, and GPIO48 joins the reserved-pin list. The claims that GPIO6 has no pull at reset and that its power-up glitch is low were never checked against the ESP32-S3 datasheet here, so both are now marked unverified, in the README and on the sheet. A validation boundary states what the N16R8 has shown (baseline validated, fan-characterization image booted, static GPIO6 levels with nothing attached) and what it has not (fixture, external stage, tach path, 25 kHz waveform; PPR unknown). The pins remain DragonBench bench-fixture assignments, not JumpJet GPIOs. The schematic, PDF and SVG are regenerated for the note text only.
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Summary
This PR adds the first experiment profile,
fan-characterization, and uses it to set up how DragonBench grows as a characterization platform. Each image is exactly one board profile plus one experiment profile. It also adds the N16R8 board profile (the selected bench mule) and makes each board's onboard RGB LED a board-owned status light.The fan profile is bench characterization equipment for the JumpJet Sanyo Denki
9GA0424P3J001candidate. It provides a PWM stimulus through an external open-drain stage and captures tach edges. It is not product fan control.Validation
Software / CI validated
-Werror), and ESP-IDF 5.3.5 builds for all three boards asbaselineand configuredfan-characterization, plus the refusal build (see Test / build matrix).Physically validated on N16R8 (one Lonely Binary
MCN16R8board, 2026-09-29;baselineimage from153c6d1, ESP-IDF 5.3.5, clean tree; no fixture, fan, GPIO6/7 wiring or 24 V connected)/api/v1/devicereportesp32s3-n16r8,baseline, the git SHA, a clean tree and ESP-IDF v5.3.5.46/4018) and used by the bootloader (DIO, 80 MHz).ready. RESET-button and bridge-RTS resets both return toready.UARTconnector (bridge,1A86:7522) handles auto-download, hash-verified flashing, RTS reset and the console log. TheUSBconnector (native,303A:1001) handles auto-download and hash-verified flashing.ready(visual, untimed).Physically validated on N16R8:
fan-characterizationno-load smoke test (same board, image fromb90e713, gate GPIO6 / sink level 1 / tach GPIO7 / PPR 0, flashed overUART; only a DMM on GPIO6, GPIO7 unconnected, no fixture, stage, fan or 24 V)experiment_profilefan-characterization,FAN_PWM_HOLDavailable,tach_pprnull, heater and fan controlfalse.static_release); 3.26 V during a 100% hold (static_sink). Readings were untimed.phase_start→phase_end→run_completeandppr/rpmnull. The status LED was off during each run and green after it.Still unvalidated
USBconnector.UARTconnector.RGBpad state.Details:
docs/TARGET_N16R8.md.Board profiles
n8r8(default)RGBlink, 5 V supplyn16r8MCN16R8on a Lonely Binary carrierRGB@IO48), no power GPIOtinys3dci/build-esp32s3.sh's board case defines each profile; everysdkconfig.defaults.*is either a board overlay or an experiment overlay, and board overlays never select an experiment.esp32s3-n16r8and configures 16 MB flash.partitions.csvis unchanged and ends below 8 MB, so the upper 8 MB is intentionally unused.docs/TARGET_N16R8.md).Status RGB LED
CONFIG_DB_STATUS_RGB_GPIO,CONFIG_DB_STATUS_RGB_POWER_GPIOandCONFIG_DB_STATUS_RGB_POWER_ACTIVE_LEVEL, each set per board (-1= none).readyevent, then solid dim green while the device is ready and idle.state_lock, before the workload task can emitphase_start. It stays off throughphase_end.CONTROLLED_REBOOT, leaves it off.db_status_ready()is a pure function, tested natively, and is the same in every experiment profile.Experiment-profile architecture
DB_EXPERIMENT_PROFILE, selects the profile. Today that isbaseline(the default, stated explicitly insdkconfig.defaults) orfan-characterization. Profiles are not independently combinable feature flags.firmware/common/include/db_experiment.his the only code that readsCONFIG_DB_EXPERIMENT_*. Everything else compiles underDB_EXPERIMENT_<NAME>.sdkconfig.defaults.<experiment>. Wiring goes in an untrackedsdkconfig.<experiment>.local.ci/build-esp32s3.sh <board> [experiment] [--expect-refusal]checks every ELF for code belonging to other experiments, and each board's flash size, PSRAM mode, identity, RF-switch and status-RGB settings.docs/EXPERIMENT_PROFILES.md, andtests/test_experiment_profiles.pyenforces them. Every non-baseline profile needs a configured hosted ESP-IDF build on every board, not only refusal checks.Fan PWM stimulus + tach capture
FAN_PWM_HOLDtakespwm_hz(10–50000),sink_duty_pct(0–100 in 0.1 steps) andduration_ms. All three are required and validated on the device.sink_duty_pctis the fraction of time the external stage sinks the fan PWM line.app_main), before every hold, at run end, on abort, on every error, and from a shutdown handler.tach_unavailable. The counter is cleared right before the measurement window opens.phase_start/fault/phase_end/run_completeevents carry the parameters, raw edge count, window timestamps and edge frequency, for correlation with external captures and DragonSniff.Static 0% / 100% endpoints
2**duty_resolutioncan overflow the duty counter (documented in the ESP-IDF 5.3.5 LEDC docs).static_release) and 100% statically at the sink level (static_sink). LEDC is used only strictly between them, and its duty value is always between 1 and2^bits − 1.Build-time exclusion from baseline images
FAN_PWM_HOLDis reportedunsupported, requests are rejected with HTTP 400, and no LEDC, PCNT or fan-characterization code is linked.Unknown PPR and evidence
"ppr": null, "rpm": null, and RPM is never derived.CONFIG_DB_FAN_TACH_PPR_EVIDENCEfails the build.Fixture wiring safeguards
Wiring is mandatory. Gate GPIO, gate sink level and tach GPIO have no defaults, and a build without them stops with one
#errorper missing setting.Unsafe pins fail the build:
Host tests run the real guards through the C preprocessor for each board.
External stage. An external open-drain stage is required.
Power-up, reset and panic safety depends on external gate/base bias hardware. The firmware never enables an internal pull on the gate.
Bench direction. The provisional Rev 0 bench wiring on the N16R8 is GPIO6 gate (non-inverting N-channel stage, sink level 1) and GPIO7 tach. That is bench wiring only, not JumpJet GPIOs, and the Rev 0 fixture (PR hardware: Rev 0 fan-characterization fixture schematic (stacked on #8) #9) is not yet built.
Device, build and measurement provenance
/api/v1/devicereportsboard_profile,experiment_profile,device_id, andbuild(firmware version,git_sha,source_treeclean/dirty/unknown, and the ESP-IDF version). The boot event carries the same identity.null/unknown; nothing is guessed.measurement_authorityis replaced bymeasurement_provenance, which maps each quantity todut.<peripheral>,derived.<rule>orexternal.dut.esp32s3_pcnt.externalunless a PPR is configured with evidence.external.heater_capabilityandfan_control_capabilityarefalsein every image."truncated": trueinstead of being cut off.CLI sweep tooling
fan-sweeprunsup,down,up-downordown-upsweeps as repeatedFAN_PWM_HOLDruns and rewrites a JSON results file after every step. Sweep logic lives only on the host.runaccepts--pwm-hzand--sink-duty-pct, andexportnow includes the device identity.JumpJet boundary
This produces characterization evidence only. It defines no JumpJet minimum duty, RPM proof threshold, fan-proof timeout, stall threshold, PWM frequency, PPR or production GPIO, and no product fan policy; a contract test guards this. JumpJet is not modified.
Test / build matrix
python-host, localtest_db_run(incl. status-light policy) andtest_db_fan, ASan/UBSan,-Werror, as baseline and fan-characterizationnative-cmatrix, localesp32s3-build, localfan-characterization-configured, localfan-characterization-refusal, localAbout the CI compile fixture: the configured fan-characterization CI job writes
sdkconfig.fan-characterization.localinside the runner workspace only.The Espressif component registry is blocked in the development environment. Local ESP-IDF builds therefore supplied the pinned
mdns-v1.12.0source from GitHub in throwaway copies. Hosted CI uses the normal registry fetch.Still needed before hardware work
See
docs/FAN_CHARACTERIZATION.mdand thedocs/TARGET_*.mdboard profiles.🤖 Generated with Claude Code
https://claude.ai/code/session_01XaHXL38BsvntY8t344vv45
Generated by Claude Code
baselineandfan-characterizationexperiment profiles. Each image combines one experiment profile with one board profile. Adds N16R8 board settings and board-owned status RGB behavior.FAN_PWM_HOLDworkload for bench characterization. It drives an external open-drain stage and captures tach edges. It does not add product fan control, closed-loop control, heater paths, or JumpJet requirements. Fixture wiring must be configured explicitly. The build rejects missing, reserved, or conflicting GPIO assignments, and requires evidence when PPR is configured.POST /api/v1/runswithpwm_hzandsink_duty_pct. Device and boot identity report board and experiment profiles, build provenance, measurement provenance, and bench-stimulus capabilities. Event storage preserves valid JSON envelopes and marks eventstruncatedwhen it omits parameters and metrics. The CLI adds orderedfan-sweepruns and incremental JSON reports.Validation / Remaining gaps
-Werror, and ESP-IDF 5.3.5 builds for all three boards in baseline and configured fan-characterization profiles, plus a build-refusal check.mdns-v1.12.0source because the development environment could not access the Espressif component registry. Hosted CI uses the registry.