A lightweight graphical FPGA development workflow tool built around OSS CAD Suite.

This is where I am putting first RISC-V RV32I single-cycle processor (in development)

A progressive, hands-on workshop for designing digital hardware using SystemVerilog on the Sipeed Tang Nano 20K (and 9K). From toolchain setup to HDMI video output — build real circuits on real hardware.

Visualize and manage your OSS CAD Suite FPGA design workflow through a simple graphical interface.