A single-cycle RV32I CPU core with machine-mode traps, verified with RISC-V Formal and Spike lockstep co-simulation, booting FreeRTOS and running CoreMark on a Basys 3 FPGA.
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Updated
Jul 31, 2026 - SystemVerilog
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riscv-formal
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This is where I am putting first RISC-V RV32I single-cycle processor (in development)
cpu fpga processor riscv rtl verilog systemverilog computer-architecture soc formal-verification yosys risc-v digital-design rv32i verilator symbiyosys cpu-core oss-cad-suite riscv-formal riscv-tests
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Updated
Jul 31, 2026 - SystemVerilog
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