Skip to content

fix(boards): correct the F412 chip selection and app flash size on ARK cannodes - #28456

Merged
dakejahl merged 10 commits into
mainfrom
dakejahl/can-flow-mr-f412vg
Sep 4, 2026
Merged

fix(boards): correct the F412 chip selection and app flash size on ARK cannodes#28456
dakejahl merged 10 commits into
mainfrom
dakejahl/can-flow-mr-f412vg

Conversation

@dakejahl

@dakejahl dakejahl commented Aug 29, 2026

Copy link
Copy Markdown
Contributor

Summary

Name the ARK cannodes after the parts they actually use — STM32F412VG on the 100-pin boards (including DIST), STM32F412CG on CANnode — give every 1MB board 960K of app flash, and open the F412 SRAM region to 256K.

Problem

Flow MR, DIST, Teseo, X20, F9P, Septentrio/MOSAIC/G5 and MAG are STM32F412VGH6 and CANnode is STM32F412CGU6, but Kconfig only listed the 48-pin 512KB CE, so all of them selected it. Note that the chip selection is not what sets the flash size — STM32_FLASH_SIZE comes from CONFIG_STM32_FLASH_CONFIG_G, which these boards already set. CE was wrong as documentation, and it capped STM32_NGPIO at 34.

Separately, the app linker scripts subtracted the 32K param window twice. App flash starts at 0x08010000 after the 64K bootloader+params reservation, so the region is 960K, not 928K; the canbootloader always computed 960K, so the two disagreed by a sector.

The linker scripts also still described the F42x 192K SRAM split, so .data/.bss could not use the upper 64K.

Solution

NuttX 12.12 already has VG/CG (PX4/NuttX#405) and ends the F412 heap at 0x20040000 (PX4/NuttX#407). Select VG/CG per board, set app flash LENGTH to 960K, set sram LENGTH to 256K on all ARK F412 cannodes (VG/CG and the remaining CE boards), and map VG/CG to a DEBUG_DEVICE. The linker comments also described an SRAM split the F412 does not have — it is one contiguous 256KB block at 0x20000000.

@github-actions github-actions Bot added kind:bug Something is broken or behaving incorrectly. scope:dependencies Dependency or submodule updates. scope:boards Board-specific changes or hardware definitions. labels Aug 29, 2026
@dakejahl dakejahl changed the title fix(can-flow-mr): use STM32F412VG and 960K app flash fix(boards): select STM32F412VG on 100-pin 1MB ARK cannodes Aug 29, 2026
@dakejahl dakejahl changed the title fix(boards): select STM32F412VG on 100-pin 1MB ARK cannodes fix(boards): correct the F412 chip selection and app flash size on ARK cannodes Aug 29, 2026
@dakejahl
dakejahl force-pushed the dakejahl/can-flow-mr-f412vg branch from fd12bf7 to 54defac Compare August 29, 2026 21:35
@dakejahl
dakejahl force-pushed the dakejahl/can-flow-mr-f412vg branch from 54defac to 324c29c Compare September 1, 2026 19:45
@dakejahl
dakejahl changed the base branch from main to dakejahl/nuttx-bump September 1, 2026 19:45
@github-actions

github-actions Bot commented Sep 1, 2026

Copy link
Copy Markdown
Contributor

🔎 FLASH Analysis

px4_fmu-v5x [Total VM Diff: 0 byte (0 %)]
    FILE SIZE        VM SIZE    
 --------------  -------------- 
  +0.0%     +55  [ = ]       0    .debug_abbrev
  -0.0%      -2  [ = ]       0    .debug_info
  -0.0%      -5  [ = ]       0    .debug_line
     +50%      +2  [ = ]       0    [Unmapped]
    -0.0%      -7  [ = ]       0    [section .debug_line]
  +0.0%     +48  [ = ]       0    TOTAL

px4_fmu-v6x [Total VM Diff: 0 byte (0 %)]
    FILE SIZE        VM SIZE    
 --------------  -------------- 
  +0.0%     +55  [ = ]       0    .debug_abbrev
  -0.0%      -2  [ = ]       0    .debug_info
  -0.0%      -5  [ = ]       0    .debug_line
     +50%      +2  [ = ]       0    [Unmapped]
    -0.0%      -7  [ = ]       0    [section .debug_line]
  +0.0%     +48  [ = ]       0    TOTAL

Updated: 2026-09-03T23:58:39

Base automatically changed from dakejahl/nuttx-bump to main September 1, 2026 20:00
@dakejahl
dakejahl force-pushed the dakejahl/can-flow-mr-f412vg branch from 324c29c to 646580f Compare September 1, 2026 20:12
@dakejahl
dakejahl marked this pull request as draft September 2, 2026 19:43
@dakejahl

dakejahl commented Sep 2, 2026

Copy link
Copy Markdown
Contributor Author

Holding off on this until the nuttx bump PR is merged

The part is STM32F412VGH6 (100-pin, 1MB), not the 48-pin 512KB CE.
App flash starts at 0x08010000 after the 64K bootloader+params window,
so the region is 960K, not 928K.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Teseo, X20, F9P, and Septentrio/MOSAIC/G5 GPS modules use
STM32F412VGH6, same as Flow MR. They were still selecting the
48-pin 512KB CE and a 928K app region that double-counted params.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The part is STM32F412CGU6, not the 512KB CE. App flash starts at
0x08010000 after the 64K bootloader+params window, so the region is
960K, not 928K.
The part is STM32F412VGH6, not the 48-pin 512KB CE, and the app region
after the 64K bootloader+params reservation is 960K, not 928K.
…ipts

The F412 has one contiguous 256KB SRAM at 0x20000000. The block list
these scripts carried is F42x boilerplate and describes memory the part
does not have.
The part is STM32F412VGH6, not the 48-pin 512KB CE. App flash starts at
0x08010000 after the 64K bootloader+params window, so the region is
960K, not 928K.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
@dakejahl
dakejahl force-pushed the dakejahl/can-flow-mr-f412vg branch from 5c9ae91 to 7a9a76c Compare September 3, 2026 21:54
@dakejahl
dakejahl marked this pull request as ready for review September 3, 2026 21:54
dakejahl and others added 4 commits September 3, 2026 16:28
NuttX now ends the F412 heap at 0x20040000. The linker scripts still
capped .data/.bss at 192K, leftover from the F42x split.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The F412 has one contiguous 256KB SRAM at 0x20000000. The block list
these scripts carried is F42x boilerplate and describes memory the part
does not have.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
PH1 is OSC_OUT for the HSE crystal. The jumper option was already
undefined, so these defines could not be enabled without stopping
the clock.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The bitbang GPIO defines did not match the schematic nets, so a bus reset would drive the wrong pins.

Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
@dakejahl
dakejahl merged commit 8f9b91b into main Sep 4, 2026
69 of 71 checks passed
@dakejahl
dakejahl deleted the dakejahl/can-flow-mr-f412vg branch September 4, 2026 01:30
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

kind:bug Something is broken or behaving incorrectly. scope:boards Board-specific changes or hardware definitions. scope:dependencies Dependency or submodule updates.

Projects

None yet

Development

Successfully merging this pull request may close these issues.

1 participant