fix(boards): correct the F412 chip selection and app flash size on ARK cannodes - #28456
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🔎 FLASH Analysispx4_fmu-v5x [Total VM Diff: 0 byte (0 %)]px4_fmu-v6x [Total VM Diff: 0 byte (0 %)]Updated: 2026-09-03T23:58:39 |
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Holding off on this until the nuttx bump PR is merged |
The part is STM32F412VGH6 (100-pin, 1MB), not the 48-pin 512KB CE. App flash starts at 0x08010000 after the 64K bootloader+params window, so the region is 960K, not 928K. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
Teseo, X20, F9P, and Septentrio/MOSAIC/G5 GPS modules use STM32F412VGH6, same as Flow MR. They were still selecting the 48-pin 512KB CE and a 928K app region that double-counted params. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The part is STM32F412CGU6, not the 512KB CE. App flash starts at 0x08010000 after the 64K bootloader+params window, so the region is 960K, not 928K.
The part is STM32F412VGH6, not the 48-pin 512KB CE, and the app region after the 64K bootloader+params reservation is 960K, not 928K.
…ipts The F412 has one contiguous 256KB SRAM at 0x20000000. The block list these scripts carried is F42x boilerplate and describes memory the part does not have.
The part is STM32F412VGH6, not the 48-pin 512KB CE. App flash starts at 0x08010000 after the 64K bootloader+params window, so the region is 960K, not 928K. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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September 3, 2026 21:54
NuttX now ends the F412 heap at 0x20040000. The linker scripts still capped .data/.bss at 192K, leftover from the F42x split. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The F412 has one contiguous 256KB SRAM at 0x20000000. The block list these scripts carried is F42x boilerplate and describes memory the part does not have. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
PH1 is OSC_OUT for the HSE crystal. The jumper option was already undefined, so these defines could not be enabled without stopping the clock. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
The bitbang GPIO defines did not match the schematic nets, so a bus reset would drive the wrong pins. Signed-off-by: Jacob Dahl <dahl.jakejacob@gmail.com>
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Summary
Name the ARK cannodes after the parts they actually use — STM32F412VG on the 100-pin boards (including DIST), STM32F412CG on CANnode — give every 1MB board 960K of app flash, and open the F412 SRAM region to 256K.
Problem
Flow MR, DIST, Teseo, X20, F9P, Septentrio/MOSAIC/G5 and MAG are STM32F412VGH6 and CANnode is STM32F412CGU6, but Kconfig only listed the 48-pin 512KB CE, so all of them selected it. Note that the chip selection is not what sets the flash size —
STM32_FLASH_SIZEcomes fromCONFIG_STM32_FLASH_CONFIG_G, which these boards already set. CE was wrong as documentation, and it cappedSTM32_NGPIOat 34.Separately, the app linker scripts subtracted the 32K param window twice. App flash starts at 0x08010000 after the 64K bootloader+params reservation, so the region is 960K, not 928K; the canbootloader always computed 960K, so the two disagreed by a sector.
The linker scripts also still described the F42x 192K SRAM split, so
.data/.bsscould not use the upper 64K.Solution
NuttX 12.12 already has VG/CG (PX4/NuttX#405) and ends the F412 heap at
0x20040000(PX4/NuttX#407). Select VG/CG per board, set app flashLENGTHto 960K, setsram LENGTHto 256K on all ARK F412 cannodes (VG/CG and the remaining CE boards), and map VG/CG to aDEBUG_DEVICE. The linker comments also described an SRAM split the F412 does not have — it is one contiguous 256KB block at 0x20000000.