Added Value

What I Did

For this project I used some parts of Altera's TV decoder demo. Specifically I used the modules that convert the Sync signals and 8 bit bus into a 16 bit bus with a ready signal. I designed my own ram using Altera's megafunction and implemented the VGA control to output video. I used the top level module from the Altera demo, called DE2_115_TV.v, as a template to wire together all of my modules. The module instantiations I reuse from the demo are unchanged but the modules I created are added into the template while the unused modules and ports are deleted to make the file neater. I also create my own Image processing module to change the video stream in real time by adding a gray box to an arbitrary location on the frame buffer. The differences between my design and the demo design are described in detail below.

Differences Between this Project and Altera's Demo

My design has some key differences from the Altera demo that this project borrowed some sample code from. The major differences include area, of-chip resources and image processing. Each of these differences is described in the sections below.

Area

This project uses fewer logic elements than Altera's example design. With less than 2900 logic elements, this design is about 5% smaller than the example design provided by Altera. The savings in area can be useful when a smaller FPGA is required due to cost or other reasons. The reduced area also makes this project easier to analyze and understand than the demo provided, making this project a better teaching tool. This project involves significantly fewer modules than the example allowing someone new to verilog to quickly understand the design without needing to convert to a different format first.

Off-chip Resources

This design does not require off chip memory, allowing it to update significantly faster then the 60Hz required for video. This project could easily be converted to act as a buffer for a different form of data, such as several channels of audio or even some SPI or I2C sensors. The fact that no off-chip resources are required makes this design more flexible than the example. The only thing required to move this design to a new FPGA would be a drop in replacement for the frame buffer memory. Altera's ram Megafunction allows a drop in replacement ram to be generated for almost all Altera FPGAs. The Example design uses the off chip DDR2 ram which in not present or the same on every development board.

Image Processing

This design allows for simple image processing, something the Altera Demo does not include. Using a filter on the frame buffer address to identify the appropriate place to write the arbitrary image will be useful in my senior design project next year. Future work will involve replacing the gray box with letters and numbers, as my senior design project will identify handwritten characters on an image and overlay print characters on top of handwritten ones and output the video to a monitor.