Composite Input
The composite video input modules used were taken from the Altera Demo in the sample code directory. Their functionality was not changed. The differences in the designs involve what and how these modules are connected to the rest of the design. Even though I did not create the modules to process the composite input, I will describe them here.
The DE2-115 includes a composite video ADC that converts the signal to a 16 bit video signal. The chip has an 8 bit output bus and outputs the video signal one byte at a time. The ADC includes horizontal and vertical sync signals similar to the ones used by the VGA module except here the signals are input to the FPGA rather than output. To understand these Sync signals, pleas read the VGA Output page of the wiki, where the signals are described in more detail.
The module that processes the composite video converts the 8 bit bus into a 16 bit bus so the logic that uses the video data does not need to wait 2 clock cycles to receive a full pixel's worth of data. The module also has a 'data valid' signal named dval that indicates that the data on the 16 bit bus is ready. The data is not ready every clock cycle because the ACD outputs a 720x400 signal while the frame buffer and VGA monitor expect a 640x480 signal. The Altera demo design also handles some of the down sampling in the models called DIV.v. This downsampling is not perfect though and leads to the vertical black lines on the screen that are spaced out by about 1cm.
Terasic. (2012, May 23). DE2 TV Decoder (Version 2.0) [Computer software]. Retrieved April 21, 2016.