How It Works
The detailed description of this project is spread out over several pages, separated by topic. A table of contents with links to these pages is below.
- General Description
- VGA Output
- Composite Input
- Image Processing and Frame Buffer
The frame buffer is implemented in on-chip ram using Altera's ram megafunction. A two port ram is used so that data can be written and read at the same time. The address being written to is checked before each write and if the address is part of the gray square on the screen, the data from the video input is replaced with a constant value. The image below shows the netlist generated by Quartus from my verilog design. The setlist image is very large and does not display well here. To get a better view try downloading the image.
